Section XII: I/O Peripheral Controllers
Chapter 66: CAN FD Controller
Bus-Off Recovery State
The controller enters the bus-off state if the transmit error count reaches or exceeds its terminalpoint. Recovery from bus-off states is governed by the auto recovery [ABR] or manual recovery[SBR] bit setting in the Mode_Select register and is done according to the protocol specification.
Note: In the case of a protocol exception or bus-off event, any pending messages/frames for transmissionsmust be canceled and re-queued for proper operation after recovering from these events.
Configuration Sequence
The following steps are for configuring the controller when it is powered on or after system orsoftware reset.
1.Choose the operating mode:
Note: The sample point position programming follows the industry standard.
•Normal—write 0s to the [LBACK], [SNOOP], and [SLEEP] bits in the MSR. Write requiredvalue for [BRS] and [DAR] fields in the Mode_Select register.•Sleep—write 1 to [SLEEP] bit and 0 to [LBACK] and [SNOOP]. Write required value for[BRS] and [DAR].•Loopback—write 1 to [LBACK] and 0 to [SLEEP] and [SNOOP] bits. Write required valuefor [BRS].•Snoop—write 1 to [SNOOP] bit and 0 to [LBACK] and [SLEEP].2.Configure the Transfer Layer Configuration registers.
IMPORTANT! For proper operation, ensure that all CAN FD nodes in the network are programmed tohave the same arbitration phase bit rate, data phase bit rate, arbitration phase sample point position,and data phase sample point position.
•Program the ArbPhase_BaudRate prescale register (nominal) and the ArbPhase_BitTimingregister (nominal) with the value calculated for the particular arbitration phase bit rate.•Program the DataPhase_BaudRate and DataPhase_BitTiming registers with the value toachieve desired data phase bit rate.
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The DataPhase_BaudRate register also contains [TDC] control field.
Note: The bit rate configured for the data phase must be higher than or equal to the bit rateconfigured for the arbitration phase. The Transfer Layer Configuration registers can be changedonly when the SW_Reset [CEN] bit is 0.
Note: For operation with ArbPhase_BaudRate [BRP] = 0 (prescalar value = 1), set both [BRP] fornominal and data phase as 1 (register value = 0). Additionally, software needs to program the Mode_Select register bit [11] as follows (equivalent to [BRP_1_EN]):
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Section XII: I/O Peripheral Controllers
Chapter 66: CAN FD Controller
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Set bit [11] = 1 when [BRP] = 1Set bit [11] = 0 when [BRP] != 1
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3.Configure the Acceptance Filter registers (AFR, AFMR, AFIR) to the following:
•Write a 0 to the UAF bit in the register corresponding to the Acceptance Filter Mask andthe ID register pair to be configured.•Write the required mask information to the Acceptance Filter Mask register.•Write the required ID information to the Acceptance Filter ID register.
•Write 1 to the UAF bit corresponding to the Acceptance Filter Mask and ID register pair.•Repeat the steps for each Acceptance Filter Mask and ID register pair.
•To enable RX buffer 1, arrange the Filter Mask and ID register as per the requirement. The[RXFP] field in the RX buffer Watermark register also needs to be set accordingly to avalue less than31d.4.Program the Interrupt Enable registers as per requirements.
5.Enable the protocol controller by writing a 1 to SW_Reset [CEN]. After the occurrence of 11
consecutive recessive bits, the controller clears the Status [CONFIG] bit to 0 and sets otherappropriate mode status bit in the Status register.
RECOMMENDED: If the [CEN] bit is cleared during the controller operation, then reset the controller, too.RECOMMENDED: The [LBACK], [SLEEP], and [SNOOP] bits should never be set to 1 at the same time.
Message Transmission
All messages written in the TX buffer should follow the required message format for ID, DLC, andDW fields described earlier. Each [RRnn] bit in the TxBuff_Ready_Req register corresponds to amessage element in the Tx buffer.Software Actions
1.Poll the TxBuff_Ready_Req register to check current pending transmission requests.2.If all bits of the TxBuff_Ready_Req register are set, a new transmission request can be added
only if:
a.One or more buffer transmission requests are canceled, orb.One or more buffer transmission completes
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Section XII: I/O Peripheral Controllers
Chapter 66: CAN FD Controller
Loopback Modes
There are two loopback types:
•Self loopback: TX output from a controller is connected to its own RX input•Controller-to-controller loopback: connects CAN controller 0 to controller 1
Self Loopback
In self-loopback mode, the controller receives the messages that it transmits using an internalcircuit from its TX signal to its RX signal. The received messages are stored in receive buffersbased on an ID match result. The transmissions are acknowledged to itself by the receiver. Thecontroller also stores the received messages (based on an ID match result). In self-loopbackmode, the controller is disconnected from the MIO multiplexer and pins.
This mode is normally used for diagnostics. The loopback mode is selected using the CANFD Mode_Select [LBACK] bit. The controller receives messages that it transmits. Received messagesare stored in receive buffers based on an ID match result. The controller also stores its owntransmitted messages (based on an ID match result).
The controller does not participate in normal bus communication and does not receive anymessages transmitted by other CAN nodes (external TX line is ignored). It drives a recessivebitstream on the CAN bus (external TX line).
Controller-to-controller Loopback
The controller-to-controller loopback connection is selected using the MIO_Loopback
[CAN0_LOOP_CAN1] control bit. When the [CAN0_LOOP_CAN1] is set = 1, these connectionsare made:
•CAN0 TX output is connected to the CAN1 RX input•CAN1 TX output is connected to the CAN0 RX input
Protocol Exception Event State
The controller enters the CAN FD protocol exception event (PEE) state if the controller receivesthe \"res\" bit as recessive in the CAN FD frame (provided MSR [DPEE] bit is not set = 1). Thecontroller exits this state after detecting a sequence of 11 nominal recessive bits on the CANbus, and as per the protocol specification, the transmit and receive error count remainsunchanged in this state.
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