FPGARAM

FPGA RAM读写RAM module input ram_clk;

input wr,rd; input cs;

output[7:0] data_out_bus; //读出数据总线 input[7:0] ram_data_bus; //写入数据总线 output[5:0] ram_addr_bus; //ram地址线 reg[7:0] data_out_bus; reg[5:0] ram_addr_bus;

reg[5:0] addr_count; //计数器计数做ram的地址 reg[7:0] mema[63:0]; integer i; initial begin

addr_count=0;

for(i=0;i<;i=i+1) //ram清0 mema<=i+1; end

always @(posedge ram_clk) if(cs==1'b1) addr_count=6'b0; else if(wr==1'b0)begin //写数据 ram_addr_bus<=addr_count;

mema[ram_addr_bus]<=ram_data_bus; addr_count<=addr_count+1'b1; end

else if(rd==1'b0)begin //读数据

ram

(ram_clk,wr,rd,cs,ram_data_bus,data_out_bus,ram_addr_bus);

ram_addr_bus<=addr_count;

//ram_data_bus_reg<=mema[ram_addr_bus]; data_out_bus<=mema[ram_addr_bus]; addr_count<=addr_count+1'b1; end

else addr_count<=6'b0; endmodule

在fpga内部实现2个双口ram，可以实现乒乓操作 library IEEE;

use IEEE.STD_LOGIC_11.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity dualportram is port (

clk : in std_logic;

--dout_1: inout std_logic_vector(7 downto 0); --dout_2: inout std_logic_vector(7 downto 0) dout : inout std_logic_vector(7 downto 0) );

end dualportram;

architecture action of dualportram is component lpmramdp_1 PORT (

data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); wren : IN STD_LOGIC := '1';

wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0); clock : IN STD_LOGIC;

q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); end component;

component lpmramdpplus PORT (

data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); wren : IN STD_LOGIC := '1';

wraddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0); clock : IN STD_LOGIC ;

q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );

end component;

signal wrCount_1 : std_logic_vector (11 DOWNTO 0); signal rdCount_1 : std_logic_vector (12 DOWNTO 0); signal dataIn_1 : std_logic_vector (15 downto 0); signal dataOut_1 : std_logic_vector (7 downto 0); signal wrCount_2 : std_logic_vector (12 DOWNTO 0); signal rdCount_2 : std_logic_vector (13 DOWNTO 0); signal dataIn_2 : std_logic_vector (15 downto 0); signal dataOut_2 : std_logic_vector (7 downto 0); signal flag:std_logic; begin process(clk) begin

if rising_edge(clk) then wrCount_1 <= wrCount_1 + 1; rdCount_1 <= rdCount_1 + 1; wrCount_2 <= wrCount_2 + 1; rdCount_2 <= rdCount_2 + 1;

flag <= not flag; if (flag = '1') then dout <= dataOut_1; else

dout <= dataOut_2; end if; end if; end process; u1: lpmramdp_1 port map (

data => dataIn_1, wren => '1',

wraddress => wrCount_1, rdaddress => rdCount_1, clock => clk,

--q => dout_1 q => dataOut_1 );

u2: lpmramdpplus PORT map (

data => dataIn_2, wren => '1',

wraddress => wrCount_2, rdaddress => rdCount_2, clock => clk,

--q => dout_2 q => dataOut_2 ); end;