SN74LV4046APWR资料

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SN74LV4046A

HIGH-SPEEDCMOSLOGICPHASE-LOCKEDLOOP

WITHVCO

SCES656A–FEBRUARY2006–REVISEDFEBRUARY2006

FEATURES

•

ChoiceofThreePhaseComparators–ExclusiveOR

–Edge-TriggeredJ-KFlip-Flop–Edge-TriggeredRSFlip-Flop

ExcellentVCOFrequencyLinearity

VCO-InhibitControlforON/OFFKeyingandforLowStandbyPowerConsumption

OptimizedPower-SupplyVoltageRangeFrom3Vto5.5V

WideOperatingTemperatureRange...–40°Cto125°C

Latch-UpPerformanceExceeds250mAPerJESD17

ESDProtectionExceedsJESD22

–2000-VHuman-BodyModel(A114-A)–200-VMachineModel(A115-A)

–1000-VCharged-DeviceModel(C101)

D, DGV, NS, OR PW PACKAGE

(TOP VIEW)

••••••

PCPOUTPC1OUTCOMPINVCOOUT

INHC1AC1BGND

12345678

161514131211109

VCC

PC3OUTSIGINPC2OUTR2R1

DEMOUTVCOIN

DESCRIPTION

TheSN74LV4046Aisahigh-speedsilicon-gateCMOSdevicethatispincompatiblewiththeCD4046BandtheCD74HC4046.ThedeviceisspecifiedincompliancewithJEDECStd7.

TheSN74LV4046Aisaphase-locked-loopcircuitthatcontainsalinearvoltage-controlledoscillator(VCO)andthreedifferentphasecomparators(PC1,PC2,andPC3).Asignalinputandacomparatorinputarecommontoeachcomparator.

Thesignalinputcanbedirectlycoupledtolargevoltagesignals,orindirectlycoupled(withaseriescapacitor)tosmallvoltagesignals.Aself-biasinputcircuitkeepssmallvoltagesignalswithinthelinearregionoftheinputamplifiers.Withapassivelow-passfilter,theSN74LV4046Aformsasecond-orderloopPLL.TheexcellentVCOlinearityisachievedbytheuseoflinearoperationalamplifiertechniques.

ORDERINGINFORMATION

TA

SOP–NSSOIC–DTSSOP–PWTVSOP–DGV

PACKAGE

ORDERABLEPARTNUMBERSN74LV4040ANSSN74LV4040ANSRSN74LV4040ADSN74LV4040ADRSN74LV4040APWSN74LV4040APWRSN74LV4040ADGVR

TOP-SIDEMARKING74LV4046ALV4046ALW046ALW046A

–40°Cto125°C

Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.

PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.

Copyright©2006,TexasInstrumentsIncorporated

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SN74LV4046A

HIGH-SPEEDCMOSLOGICPHASE-LOCKEDLOOPWITHVCO

SCES656A–FEBRUARY2006–REVISEDFEBRUARY2006

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PINDESCRIPTION

PINNO.

123456710111213141516

SYMBOLPCPOUTPC1OUTCOMPINVCOOUTINHC1AC1BGNDVCOINDEMOUT

R1R2PC2OUTSIGINPC3OUTVCC

NAMEANDFUNCTION

PhasecomparatorpulseoutputPhasecomparator1outputComparatorinputVCOoutputInhibitinput

CapacitorC1connectionACapacitorC1connectionBGround(0V)VCOinput

DemodulatoroutputResistorR1connectionResistorR2connectionPhasecomparator2outputSignalinput

Phasecomparator3outputPositivesupplyvoltage

AbsoluteMaximumRatings(1)

overoperatingfree-airtemperaturerange(unlessotherwisenoted)

MIN

VCCVIVOIIKIOKIOICC

DCsupplyvoltagerangeInputvoltagerangeOutputvoltagerangeInputclampcurrentOutputclampcurrentContinuousoutputcurentDCVCCorgroundcurrent

Dpackage

θJA

Packagethermalimpedance(2)

DGVpackageNSpackagePWpackage

Tstg(1)(2)

Storagetemperaturerange

–65

VI<0VO<0VO=0toVCC

–0.5–0.5–0.5

MAX

7

VCC+0.5VCC+0.5

–20–50±35±7073120108150

°C°C/WUNITVVVmAmAmAmA

Stressesbeyondthoselistedunder\"absolutemaximumratings\"maycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder\"recommendedoperatingconditions\"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7.

RecommendedOperatingConditions

PARAMETER

TAVCCVI,VO

Operatingfree-airtemperatureSupplyvoltage

DCinputoroutputvoltage

MIN–4030

MAX1255.5VCC

UNIT°CVV

2

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SN74LV4046A

HIGH-SPEEDCMOSLOGICPHASE-LOCKEDLOOP

WITHVCO

SCES656A–FEBRUARY2006–REVISEDFEBRUARY2006

ElectricalSpecifications

PARAMETER

VCOVIHVIL

High-levelinputvoltageLow-levelinputvoltageHigh-leveloutputvoltage

INHINH

CMOSTTL

VCOOUT

CMOSTTL

C1A,C1B

(testpurposesonly)

II

InputleakagecurrentR1range(1)R2range(1)

C1capacitancerangeOperatingvoltagerange

PhaseComparatorVIHVIL

DC-coupledhigh-levelinputvoltage

DC-coupledlow-levelinputvoltageHigh-leveloutputvoltage

PCPOUT,PCNOUT

SIGIN,COMPINSIGIN,COMPINCMOSTTLCMOSTTL

IIIOZRI

Inputleakagecurrent3-stateoff-statecurrentInputresistance

SIGIN,COMPINPC2OUTSIGIN,COMPIN

VCCorGNDVILorVIH

VIatself-biasoperating

point,VI=0.5VRS>300kΩ,Leakagecurrentcaninfluence

VDEMOUTVI=VVCOIN=VCC/2,ValuestakenoverRS

rangePins3,5,and14atVCC,Pin9atGND,IIatpins3and14tobeexcludedVILorVIH

4–0.05

VILorVIH

–6–120.02

3to3..5to5.53to3..5to5.53to5.53to3..5to5.53to3..5to5.54.5to5.53to3..5to5.53to5.534.53to3..5to5.53to3..5to5.55.5

5050

±30±20

50

mV

800250

300300

kΩ

VCC–0.1

2.483.8

0.10.10.4±11±29±5

µAµAkΩVV

VCC×0.7VCC×0.7

VCC×0.3VCC×0.3

V

VCOIN

OvertherangespecifiedforR1forlinearity(2)

INH,VCOIN

VCCorGNDVILorVIH

–0.05–120.051212

3to3..5to5.53to5.54.5to5.53to3..5to5.54.5to5.53to3..5to5.54.5to5.54.5to5.55.53to5.53to4.53to3..5to5.53to3..5to5.5

3340401.11.1VCC–0.1VCC–0.1

3.8

0.10.10.550.65±15050NoLimit

1.93.2

µAkΩkΩpFVVV

VILorVIH

VCC×0.7VCC×0.7

VCC×0.3VCC×0.3

VV

TESTCONDITIONSVI(V)

IO(mA)

VCC(V)

MIN

TYP

MAX

UNIT

VOHVCOOUT

VOL

Low-level

outputvoltage

VOH

VOL

Low-level

outputvoltage

PCPOUT,PCNOUT

DemodulatorRS

Resistorrange

VOFFOffsetvoltageVCOINtoVDEM

ICC(1)(2)

QuiescentdevicecurrentµA

ThevalueforR1andR2inparallelshouldexceed2.7kΩ.

ThemaximumoperatingvoltagecanbeashighasVCC–0.9V;however,thismayresultinanincreasedoffsetvoltage.

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SN74LV4046A

HIGH-SPEEDCMOSLOGICPHASE-LOCKEDLOOPWITHVCO

SCES656A–FEBRUARY2006–REVISEDFEBRUARY2006

www.ti.com

SwitchingSpecifications

CL=50pF,Inputtr,tf=6ns

PARAMETER

PhaseComparatortPLH,tPHLtPLH,tPHLtPLH,tPHLtTHL,tTLHtPZH,tPZLtPHZ,tPLZ

PropagationdelayPropagationdelayPropagationdelayOutputtransitiontime3-stateoutputenabletime3-stateoutputdisabletimeAC-coupledinputsensitivity

VCO∆f/∆T

Frequencystabilitywithtemperaturechange

VI=VCOIN=1/2VCC,

R1=100kΩ,R2=∞,C1=100pF

C1=50pF,R1=3.5kΩ,R2=∞C1=0pF,R1=9.1kΩ,R2=∞C1=40pF,R1=3kΩ,R2=∞,VCOIN=VCC/2C1=100pF,R1=100kΩ,R2=∞C1=1nF,R2=220kΩC1=100pF,C2=100pF,R1=100kΩ,R2=∞,R3=100kΩ

3to3..5to5.53to3..5to5.53to3..5to5.53to3..5to5.53to3..5to5.53to3..5to5.5

34.5

712

0.110.112424383810170.40.44004008330

mV/kHz%MHzMHz%/°C

SIGIN,COMPINtoPC2OUT

SIGIN,COMPINtoPC2OUT(P-P)atSIGINorCOMPIN

VI(P-P)

SIGIN,COMPINtoPC1OUT

SIGIN,COMPINtoPCPOUT

SIGIN,COMPINtoPC3OUT

3to3..5to5.53to3..5to5.53to3..5to5.53to3..5to5.53to3..5to5.53to3..5to5.53to3..5to5.5

1115

13550300602005075152705432065

nsnsnsnsnsnsmV

TESTCONDITIONS

VCC(V)

MIN

TYP

MAX

UNIT

fMAX

Maximumfrequency

Centerfrequency(duty50%)

∆fVCOFrequencylinearityOffsetfrequency

kHz

Demodulator

VOUTvsfIN

4

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SN74LV4046A

HIGH-SPEEDCMOSLOGICPHASE-LOCKEDLOOP

WITHVCO

SCES656A–FEBRUARY2006–REVISEDFEBRUARY2006

APPLICATIONINFORMATION

AVERAGEOUTPUTVOLTAGE

vs

INPUTPHASEDIFFERENCE

VCC

VCC

AVERAGEOUTPUTVOLTAGE

vs

INPUTPHASEDIFFERENCE

VDEMOUT (AV)VDEMOUT (AV)

1/2 VCC1/2 VCC

005

905

φDEMOUT

1805

0

–3605

05

φDEMOUT

3605

Figure1.PhaseComparator1:

VDEMOUT=VPC1OUT=(VCC/π)(SIGIN–COMPIN);

DEMOUT=(SIGIN–COMPIN)

SIGIN

Figure2.PhaseComparator2:

VDEMOUT=VPC2OUT=(VCC/4)(SIGIN–COMPIN);

DEMOUT=(SIGIN–COMPIN)

SIGINCOMPINVCOOUTPC2OUTHigh-Impedance Off StateVCCGND

COMPINVCOOUTPC1OUT

VCCGND

VCOINPCPOUT

VCOIN

Figure3.TypicalWaveformsforPLLUsingPhaseComparator1,LoopLockedatfo

AVERAGEOUTPUTVOLTAGE

vs

INPUTPHASEDIFFERENCE

VCC

VDEMOUT(AV)

SIGINCOMPINVCOOUTPC3OUTVCOIN

Figure4.TypicalWaveformsforPLLUsingPhaseComparator2,LoopLockedatfo

1/2 VCC

VCCGND

005

1805

fDEMOUT

3605

Figure5.PhaseComparator3:

VDEMOUT=VPC3OUT=(VCC/2π)(SIGIN–COMPIN);

DEMOUT=(SIGIN–COMPIN)

Figure6.TypicalWaveformsforPLLUsingPhaseComparator3,LoopLockedatfo

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SN74LV4046A

HIGH-SPEEDCMOSLOGICPHASE-LOCKEDLOOPWITHVCO

SCES656A–FEBRUARY2006–REVISEDFEBRUARY2006

www.ti.com

APPLICATIONINFORMATION(continued)

SIGIN, COMPIN

Inputs

VStPHLPCPOUT, PC1OUT,

PC3OUTOutputs

tTHLtPLHSIGINInputsVSCOMPINInputstPZHVStTLHPC2OUTOutputVStPHZtPZL90%VStPLZ10%Figure7.Input-to-OutputPropagationDelaysand

OutputTransitionTimes

Figure8.3-StateEnableandDisableTimesforPC2OUT

CPD(1)

CHIPSECTION

Comparator1VCO(1)

R1between3kΩand50kΩR2between3kΩand50kΩR1+R2parallelvalue>2.7kΩC1>40pF

CPD120120

UNITpF

6

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PACKAGEOPTIONADDENDUM

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13-Feb-2006

PACKAGINGINFORMATION

OrderableDeviceSN74LV4046ADSN74LV4046ADGVRSN74LV4046ADRSN74LV4046ANSSN74LV4046ANSRSN74LV4046APWSN74LV4046APWR

(1)

Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE

PackageTypeSOICTVSOPSOICSOSOTSSOPTSSOP

PackageDrawing

DDGVDNSNSPWPW

PinsPackageEcoPlan(2)

Qty16161616161616

40

Green(RoHS&noSb/Br)

Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU

MSLPeakTemp(3)Level-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIM

2000Green(RoHS&

noSb/Br)2500Green(RoHS&

noSb/Br)50

Green(RoHS&noSb/Br)

2000Green(RoHS&

noSb/Br)90

Green(RoHS&noSb/Br)

2000Green(RoHS&

noSb/Br)

Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.

LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.

NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.

PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.

(2)

EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.

Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.

Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.

Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)

(3)

MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.

ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.

InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.

Addendum-Page1

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MECHANICAL DATAMPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000DGV (R-PDSO-G**) 24 PINS SHOWN0,230,1313PLASTIC SMALL-OUTLINE 0,40240,07M0,16 NOM4,504,306,606,20Gage Plane0,250°–ā8°1A120,750,50Seating Plane1,20 MAX0,150,050,08PINS **DIMA MAXA MIN143,703,50163,703,50205,104,90245,104,90387,907,704,809,605611,4011,204073251/E 08/00NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.Falls within JEDEC:24/48 Pins – MO-15314/16/20/56 Pins – MO-194POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com

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MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 MECHANICAL DATA PW (R-PDSO-G**) 14 PINS SHOWNPLASTIC SMALL-OUTLINE PACKAGE0,651480,300,190,10M0,15 NOM4,504,306,606,20Gage Plane0,251A70°–8°0,750,50Seating Plane1,20 MAX0,150,050,10PINS **DIMA MAX83,10145,10165,10206,60247,902,80A MIN2,904,904,906,407,709,6040400/F 01/97NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion not to exceed 0,15.Falls within JEDEC MO-153POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com

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