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专利名称：Process for fabricating semiconductor
integrated circuit device, and exposingsystem and mask inspecting method to beused in the process
发明人：Yoshihiko Okamoto,Noboru Moriuchi申请号：US08/483983申请日：19950607公开号：US05667941A公开日：19970916
摘要：Herein disclosed is an exposure technology for a semiconductor integratedcircuit device which has a pattern as fine as that of an exposure wavelength. Thetechnology contemplates to improve the resolution characteristics of the pattern bymaking use of the mutual interference of exposure luminous fluxes.
申请人：HITACHI, LTD.
代理机构：Fay, Sharpe, Beall, Fagan, Minnich & McKee
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