adp3204

FEATURESPin Selectable 1-, 2-, or 3-Phase OperationStatic and Dynamic Current Sharing CharacteristicsBackward Compatible to IMVP-IISuperior Load Transient Response with ADOPT®Analog Devices’ Optimal Positioning TechnologyNoise-Blanking for Speed and StabilitySynchronous Rectifier Control Extends Battery LifeSmooth Output Transition During VID Code ChangeCycle-by-Cycle Current LimitingHiccup or Latched Overload ProtectionTransient-Glitch-Free Power GoodSoft Start Eliminates Power-On In-Rush Current SurgeTwo-Level Overvoltage and Reverse VoltageProtectionAPPLICATIONSIMVP-II and IMVP-III Core DC-to-DC ConvertersFixed Voltage Mobile CPU Core DC-to-DC ConvertersNotebook/Laptop Power SuppliesProgrammable Output Power SuppliesGENERAL DESCRIPTIONThe ADP3204 is a 1-, 2-, or 3-phase hysteretic peak currentdc-to-dc buck converter controller dedicated to power a mobileprocessor’s core. The optimized low voltage design is poweredfrom the 3.3 V system supply. The nominal output voltage isset by a 5-bit VID code. To accommodate the transition timerequired by the newest processors, the ADP3204 featureshigh speed operation to allow a minimized inductor size thatresults in the fastest change of current to the output. Tofurther allow for the minimum number of output capacitorsto be used, the ADP3204 features active voltage positioningwith ADOPT optimal compensation to ensure a superiorload transient response. The output signals interface with amaximum of three ADP3415 MOSFET drivers that areoptimized for high speed and high efficiency for driving both thetop and bottom MOSFETs of the buck converter. TheADP3204 is capable of controlling the synchronous rectifiers toextend battery lifetime in light load conditions.ADOPT is a trademark of Analog Devices, Inc.*Protected by U.S.Patent No. 5,969,657; other patents pending.

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Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties thatmay result from its use. No license is granted by implication or otherwiseunder any patent or patent rights of Analog Devices.

3-Phase IMVP-II and IMVP-IIICore Controller for Mobile CPUsADP3204*FUNCTIONAL BLOCK DIAGRAMVCCHYSSETADP3204DSHIFTVRBSHIFTHYSTERESISDPRSHIFTSETTINGBOMANDDPSLPDPRSLPSHIFT-MUXPHASEOUT3SPLITTEROUT2OUT1CS3CLIMCS2CURRENTCS1SENSEMUXCS+ENCORE CS–RAMPREGVID4VID3VID2VID5-BIT VIDVID1MUXDACANDANDVID0REGFIXEDDPRSLPREFDACOUTVIDGENDACRAMPPLPMSLRSOPPVRBDDBOMVID TRANSIENTCOREGD MONITORDETECTOR ANDCOREFBDPSLPSHIFT SELECTOR SS-HICCUP TIMERAND OCPSSDPRSLPPWRGD BLANKERSR CONTROLPWRGDDRVLSDENABLE UVLO-MAIN BIASOVP AND RVPSDPM MODULECLAMPGNDOne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 www.analog.comFax: 781/326-8703© Analog Devices, Inc., 2002

ADP3204–SPECIFICATIONS V

ParameterSUPPLY-UVLO-SHUTDOWNNormal Supply CurrentUVLO Supply CurrentShutdown Supply CurrentUVLO ThresholdVCCHVCCLUVLO HysteresisShutdown Threshold(CMOS Input)POWER GOODCore Feedback Threshold VoltageVCCHYSVSDTHVCOREFBHSymbolICCICCUVLOICCSD1 (0°C Յ TA Յ 100°C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, VCOREFB =

100k⍀, COUT1 = COUT2 = COUT3 =10 pF, CSS = 0.047 ␮F, RPWRGD = 680 ⍀ to 1.2 V, RCLAMP = 5.1 k⍀ to VCC, HYSSET, BSHIFT, DSHIFT, and

DPRSHIFT are open, BOM = H, DPSLP = H, DPRLP = L, unless otherwise noted.) Current sunk by a pin has a positive sign, sourced by a pin has anegative sign. Negative sign is disregarded for min and max values.

ConditionsMinTyp7SD = L, 3.0 V ≤ VCC ≤ 3.6 VSD = HVCC ramping up, VSS = 0 VVCC ramping down,VSS floating702.952.6055VCC/20.9 V < VDAC < 1.675 VVCOREFB ramping upVCOREFB ramping downVCOREFB ramping upVCOREFB ramping downVCOREFB = VDACOUTVCOREFB = 0.8 VDACOUTMax11425UnitmA␮A␮AVVmVVDAC (VDACOUT), VREG = VCS– = VVID = 1.25 V, CDACRAMP = 100 pF, ROUT1 = ROUT2 = ROUT3 =

Power Good Output Voltage(Open-Drain Output)Masking Time2SOFT START/HICCUP TIMERCharge/Discharge CurrentSoft Start Enable/HiccupTermination ThresholdSoft Start Termination/HiccupEnable ThresholdVID DACVID Input Threshold(CMOS Inputs)VID Input Current(Internal Active Pull-Up)Output VoltageAccuracySettling TimeDACRAMP Inner Resistance5VPWRGDtPWRGDMSK3ISSVSSENVSSTERM1.12 VDAC1.10 VDAC0.88 VDAC0.86 VDAC0.95 VCC0100–551.22001.702.00VCC/21.14 VDAC1.12 VDAC0.90 VDAC0.88 VDACVCC0.8VVVVVV␮s␮A␮AVSS = 0 VVSS = 0.5 VVREG = 1.25 V,VRAMP = VCOREFB = 1.27 VVSS ramping downVRAMP = VCOREFB = 1.27 VVSS ramping up3002.25mVVV␮AVVID0..4IVID0..4VDAC⌬VDAC/VDACtDACS4RDACRAMPVID0 to VID4 = LSee VID Code, Table 11.750 V ≥ VDAC ≥ 0.850 V0.825 V ≥ VDAC ≥ 0.600 VCDACRAMP = 100 pFCDACRAMP = 1 nF0.600–1.0–8.5851.750+1.0+8.53.52510V%mV␮s␮sk⍀–2–REV. 0

ADP3204

ParameterCORE COMPARATORInput Offset Voltage (Ramp-Reg)Input Bias CurrentOutput Voltage (OUT1, OUT2, and OUT3)Propagation Delay TimeRise and Fall Time (OUT1, OUT2, and OUT3)Noise Blanking TimeCURRENT LIMIT COMPARATORInput Offset VoltageInput Bias CurrentPropagation Delay TimeCURRENT SENSEMULTIPLEXERTrans-ResistanceCommon-Mode Voltage RangeHYSTERESIS SETTINGHysteresis CurrentSymbolVCOREOSIREG, IRAMPVOUT_HVOUT_LtRMPOUT_PD6tOUT_R7tOUT_F7tBLNKConditionsVREG = 1.25 VVREG = VRAMP = 1.25 VVCC = 3.0 VVCC = 3.6 VTA = 25°CTA = Full RangeOUT L-H TransitionOUT H-L TransitionVCS– = 1.25 VVCS+ = 1.25 VTA = 25° CTA = Full RangeMinTyp±1.5±12.5035457770130±1–355653.00.4MaxUnitmV␮AVVnsnsnsnsnsnsmV␮AnsnsVCLIMOSICS+, ICS–tCLPD6RCS1–CS+,RCS2–CS+,RCS3–CS+MUX switch is ONMUX switch is OFFVCS1 = VCS2 = VCS3VREG = 1.25 VVRAMP = 1.23 VIHYSSET = 10 ␮AIHYSSET = 100 ␮AVRAMP = 1.27 VIHYSSET = 10 ␮AIHYSSET = 100 ␮A0150502⍀M⍀VIRAMP_H,–ICS+_H–8–85885–10–10010100VDAC–12–11512115␮A␮A␮A␮AVHysteresis Reference VoltageCURRENT LIMIT SETTINGHysteresis CurrentVHYSSETICS–VRAMP = 1.23 VVREG = VCS– = VCOREFB = 1.25 VVCS+ = 1.23 VIHYSSET = 10 ␮AIHYSSET = 100 ␮AVCS+ = 1.27 VIHYSSET = 10 ␮AIHYSSET = 100 ␮AVCS+ = 1.23 V, BOM = L–27–270–18–180–31.5–36–301.5–333–21.5–25–201.5–223␮A␮A␮A␮AREV. 0–3–

ADP3204

ParameterSHIFT SETTINGBattery-Shift CurrentBattery-Shift Reference VoltageDeep Sleep-Shift CurrentDeep Sleep-Shift ReferenceVoltageDeeper Sleep-Shift CurrentSymbolIRAMPB, ICS+BVBSHIFTIRAMPD, ICS+DVDSHIFTIREGDPRICOREFBDPR8VDPRSHIFTIDPRSHIFT = –100 µA, DPRSLP=HVVID = 1.25 V,IDPRSHIFT = –100 µA,DPRSLP=H–90110VVID = 1.25 VIDSHIFT = –100 µA, BOM = HDPSLP = L–92.5ConditionsVVID = 1.25 VIBSHIFT = –100 µA, BOM = LDPSLP = HMin–92.5Typ–100VDAC–100VDAC–100130VDAC–110150–107.5Max–107.5UnitmAVmAVµAµAVDeeper Sleep-Shift ReferenceVoltageSHIFT CONTROL INPUTSBOM Threshold(CMOS Input)DPSLP Threshold(CMOS Input)DPRSLP Mode Threshold8(CMOS Input)LOW SIDE DRIVE CONTROLOutput Voltage (CMOS Output)Output CurrentVBOMVDSLPVDPRSLPVCC/2VCC/2VCC/2VVVVDRVLSDIDRVLSDDPRSLP = HDPRSLP = LDPRSLP = H, VDRVLSD = 1.5 VDPRSLP = L, VDRVLSD = 1.5 V00.7 VCC+0.4–0.40.4VCCVVmAmAOVER/REVERSE VOLTAGEPROTECTION CORE FEEDBACKOvervoltage ThresholdVCOREFB, OVP9Reverse-Voltage ThresholdVCOREFB, RVP9Output CurrentICLAMP(Open-Drain Output)VCOREFBVCOREFBVCOREFB = 2.2 V, VCLAMP = 1.5 VVCOREFB = VDAC, VCLAMP = 1.5 V2.0–0.31026VVµAmANOTES1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.2 Two test conditions: 1) PWRGD is OK but forced to fail by applying an out-of-the-Core Good-window voltage (VCOREFB, BAD = 1.0 V at VVID = 1.25 V setting) to theCOREFB pin right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking delaytime. 2) PWRGD is forced to fail (VCOREFB, BAD = 1.0 V at VVID = 1.25 V setting) but gets into the Core Good-window (VCOREFB, GOOD = 1.25 V) right after the momentthat BOM or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified blanking delay time.3Guaranteed by design4 Measured from 50% of VID code transition amplitude to the point where VDACOUT settles within ±1% of its steady state value.5Measured between DACRAMP and DACOUT pins.6 40 mVpp amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.7 Measured between the 30% and 70% points of the output voltage swing.8DPRSLP circuit meets the minimum 30 ns DPRSLPVR signal assertion requirement; guaranteed by design.9COREFB pin has a resistor divider to GND whose resistance is 41.3 k⍀ (typ), guaranteed by design.–4–REV. 0

ADP3204

ABSOLUTE MAXIMUM RATINGS*

Input Supply Voltage (VCC) . . . . . . . . . . . . . . .–0.3 V to +7 VAll Other Inputs/Outputs . . . . . . . . . . . .–0.3 V to VCC + 0.3 VJunction Temperature Range . . . . . . . . . . . . . .0°C to +150°CJunction to Air Thermal Resistance (θJA) . . . . . . . . . . .98°C/WStorage Temperature Range . . . . . . . . . . . . .–65°C to +150°CLead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .300°C*This is a stress rating only; operation beyond these limits can cause the device tobe permanently damaged.ORDERING GUIDEModelTemperatureRangePackageDescriptionLFCSP-32LFCSP-32PackageOptionCP-32CP-32Quantityper Reel50001500ADP3204JCP-REEL0ºC to 100ºCADP3204JCP-REEL70ºC to 100ºCTable I. VID CODEVID400000000000000001111111111111111VID300000000111111110000000011111111VID200001111000011110000111100001111VID100110011001100110011001100110011VID001010101010101010101010101010101VOUT1.7501.7001.6501.6001.5501.5001.4501.4001.3501.3001.2501.2001.1501.1001.0501.0000.9750.9500.9250.9000.8750.8500.8250.8000.7750.7500.7250.7000.6750.6500.6250.600CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readilyaccumulate on the human body and test equipment and can discharge without detection. Although theADP3204 features proprietary ESD protection circuitry, permanent damage may occur on devicessubjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommendedto avoid performance degradation or loss of functionality.REV. 0–5–

ADP3204

PIN CONFIGURATIONDPRSHIFTHYSSETBSHIFTDSHIFT32 31 30 29 28 27 26 25VID41VID32VID23VID14VID05BOM6DPSLP7DPRSLP8REG DACRAMPCS+CS–RAMP24VCC23CS322CS221CS120OUT319OUT218OUT117GNDPIN 1IDENTIFIERADP3204TOP VIEW(Not to Scale) 9 10 11 12 13 14 15 16 PWRGD DRVLSD CLAMP COREFB SDPIN FUNCTION DESCRIPTIONSPin1–5MnemonicVID[4:0]FunctionVoltage Identification Inputs. These are the VID inputs for logic control of the programmedreference voltage that appears at the DACOUT pin, and, via external component configura-tion, is used for setting the output voltage regulation point. The VID pins have a specified internalpull-up current that, if left open, will default the pins to a logic high state. The VID code does not setthe DAC output voltage directly but through a transparent latch that is clocked by the BOM pin’sGMUXSEL signal rising and falling edge.Battery Optimized Mode Control (Active Low). This digital input pin corresponds to the system’sGMUXSEL signal that corresponds to Battery Optimized Mode of the CPU operation in its activelow state and Performance Optimized Mode (POM) in its deactivated high state. The signal alsocontrols the optimal positioning of the core voltage regulation level by offsetting it downward inBattery Optimized Mode according to the functionality of the BSHIFT and RAMP pins. It is alsoused to initiate a masking period for the PWRGD signal whenever a GMUXSEL signal transition occurs.Deep Sleep Mode Control (Active Low). This is a digital input pin corresponding to the system’sSTPCPU signal that, in its active state, corresponds to Deep Sleep Mode of the CPU operation,which is a subset operating mode of either BOM or POM operation. The signal controls the optimalpositioning of the core voltage regulation level by offsetting it downward according to the function-ality of the DSHIFT and RAMP pins.Deeper Sleep Mode Control (Active High). This is a digital input pin corresponding to the system’sDPRSLPVR signal corresponding to Deeper Sleep Mode of the CPU operation. When the signalwhen it is activated it controls the DAC output voltage by disconnecting the VID signals from theDAC input and setting a specified internal Deeper Sleep code instead. At de-assertion of the DPRSLPVRsignal, the DAC output voltage returns to the voltage level determined by the externalVID code.The DPRSLPVR signal is also used to initiate a blanking period for the PWRGD signal to disable itsresponse to a pending dynamic core voltage change that corresponds to the VID code transition.Power Good (Active High). This open-drain output pin, via the assistance of an external pull-upresistor to the desired voltage, indicates that the core voltage is within the specified toleranceof the VID programmed value, or else is in a VID transition state as indicated by a recent statetransition of either the BOM or DPRSLP pins. PWRGD is deactivated (pulled low) when the IC isdisabled in UVLO mode, or starting up, or the COREFB voltage is out of the core power-goodwindow. The open-drain output allows external wired ANDing (logical NORing) with other opendrain/collector power-good indicators.Shutdown (Active Low). This is a digital input pin coming from a system signal that, in its activestate shuts down the IC operation, placing the IC in its lowest quiescent current state for maximumpower savings.6BOM7DPSLP8DPRSLP9PWRGD10SD–6–

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ADP3204

PIN FUNCTION DESCRIPTIONS (continued)Pin11MnemonicCLAMPFunctionClamp (Active High). This is open-drain output pin, via the assistance of an external pull-upresistor, indicates that the core voltage should be clamped for its protection. To allow the highestlevel of protection, the CLAMP signal is developed using both a redundant reference and a redun-dant feedback path with respect to those of the main regulation loop. In a preferred and moreconservative configuration, the core voltage is clamped by an external FET. The initial protectionfunction is served when it is activated by detection of either an overvoltage or a reverse-voltagecondition on the COREFB pin. Due to loss of the latched signal at IC power-off, a backup protec-tion function is served by connecting the pull-up resistor to a system “ALWAYS” regulator output(e.g., V5_ALWAYS). If the external FET is used, this implementation will keep the core voltageclamped until the ADP3204 has power reapplied, thus keeping protection for the CPU even after ahard-failure power-down and restart (e.g., a shorted top or bottom FET).Drive-Low Shutdown (Active Low). In its active state, this digital output pin indicates that thelower FET of the core VR should be disabled. In the suggested application schematic, this pin isdirectly connected to the pin of the same name on the ADP3415 or other driver IC. Drive-lowshutdown is normally activated by the DPRSLP signal corresponding to a light load condition, but anumber of dynamic conditions can override the control of this pin as needed.Soft Start. The output of this analog I/O pin is a controlled current source used to charge ordischarge an external grounded capacitor; the input is the detected voltage that is indicative ofelapsed time. The pin controls the soft start time of the IC as well as the hiccup cycle time duringoverload, including but not limited to short circuit. Hiccup operation was added to reduce shortcircuit power dissipation by more than an order of magnitude, while still allowing an automaticrestart when the failure mode ceased. The hiccup operation can be overwritten and changed tolatched-off operation by clamping the SS pin voltage to a voltage level somewhere above ~ 0.2 V.In this configuration, the controller does not restart after a hiccup cycle is initiated, but stays latched off.Core Feedback. This high impedance analog input pin is used to monitor the output voltage forsetting the proper state of the PWRGD and CLAMP pins. It is generally recommended to RC-filterthe noise from the monitored core voltage, as suggested by the application schematic.DAC Output Ramp Rate Setting. The rate at which the DAC output voltage can ramp up or downfrom one voltage to another when the VID code changes can be controlled by an externalDACRAMP capacitor connected from this pin to the DACOUT pin. The time constant of theDACOUT voltage variation is determined by the internal resistance appearing across theDACRAMP and DACOUT pins, and the capacitance of the DACRAMP capacitor. Not having anyDACRAMP capacitor connected to these pins results in the fastest rate. Use of the DACRAMP ratecontrol and the Deeper Sleep Shift adjustment features are exclusive.Digital-to-Analog Converter Output of the VID input. This output voltage is the VID controlledreference voltage whose primary function is to determine the output voltage regulation point.GroundOutputs to Driver 1–3. These digital output pins are used to command the state of theswitchednodes via the drivers. They should be connected to the IN pin of the drivers of the appropriate channels.Current Sense, Channel 1. This high impedance analog input pin is used for providing negativefeedback of the current information for the first channel.Current Sense, Channel 2. This high impedance analog input pin is used to provide negativefeedback of the current information for the second channel. The pin is also used to determinewhether the chip is acting as a single or a multiphase controller. If the CS2 pin is tied to VCC butnot to a sense resistor, then three-phase operation is disabled. In this condition, the second phaseoutput signal (OUT2) is not switching but stays static low; the first and third phase output signals(OUT1 and OUT2) are switching in phase. It’s the user’s discretion to use only one or both of thetwo signals to drive a single- or dual-channel power stage.Current Sense, Channel 3. This high impedance analog input pin is used to provide negativefeedback of the current information for the third channel. The pin is also used to determinewhether the chip is acting as a dual- or three-phase controller. If the pin is tied to VCC but not to asense resistor, then three-phase operation is disabled; the chip works as a dual-phase controller. Inthis condition, the third phase output signal (OUT3) is not switching but stays static low; the firstand second phase output signals (OUT1, OUT2) are interleaved out-of-phase signals. In single-phase operation, CS3 should be left open instead of being tied to VCC.–7–

12DRVLSD13SS14COREFB15DACRAMP161718–202122DACOUTGNDOUT1–3CS1CS223CS3REV. 0

ADP3204

PIN FUNCTION DESCRIPTIONS (continued)Pin2425MnemonicVCCRAMPFunctionPower Supply. This should be connected to the system’s 3.3 V power supply output.Regulation Ramp Feedback Input. The RAMP pin voltage is compared against the REG pin forcycle-by-cycle switching response. Several switched current sources also appear at this input: thecycle-by-cycle hysteresis-setting switched current programmed by the HYSSET pin, the BOM shiftcurrent programmed by the BSHIFT pin, and the Deep Sleep shift current programmed by theDSHIFT pin. The external resistive termination at this pin sets the magnitude of the hysteresisapplied to the regulation loop.Regulation Voltage Summing Input. This is a high impedance analog input pin into which thevoltage reference of the feedback loop allows the summing of both the DACOUT voltage and thecore voltage for programming the output resistance of the core voltage regulator. This is also the pinat which an optimized transient response can be tailored using Analog Devices’ patented ADOPTdesign technique.Current Limit Positive Sense. This high impedance analog I/O pin is multiplexed between either ofthe three current-sense inputs during the high state of the OUT pin of the respective channel.During the common off-time of both channels, the pin voltage reflects the average of the threechannels. The multiplexed current sense signal is passed to the core comparator through an externalresistive termination connected from this pin to the RAMP pin. The external (RAMP) resistor setsthe magnitude of the hysteresis applied to the regulation loop.Current Limit Negative Sense. This high impedance analog input pin which is normally Kelvinconnected to the negative node of the current sense resistor(s) via a current-limit programmingresistor. A hysteretically-controlled current—three times the current programmed at the HYSSETpin—also flows out of this pin and develops a current-limit-setting voltage across that resistor, whichmust then be matched by the inductor current flowing in the current sensing resistor in order totrigger the current limit function. When triggered, the current flowing out of this pin is reduced totwo-thirds of its previous value, producing hysteresis in the current limiting function.Hysteresis Set. This is an analog I/O pin whose output is the VID reference voltage and whose inputis a current that is programmed by an external resistance to ground. The current is used in the IC toset the hysteretic currents for the Core Comparator and the Current Limit Comparator. Modifica-tion of the resistance will affect both the hysteresis of the feedback regulation, and the current limitset point and hysteresis.Deep Sleep Shift. This is an analog I/O pin whose output is the VID reference voltage and whoseinput is a current that is programmed by an external resistance to ground. The current is used in theIC to set a switched bias current out of the RAMP pin, depending on whether it is activated by theDSLP signal. When activated, this added bias current creates a downward shift of the regulated corevoltage to a predetermined optimum level for regulation corresponding to Deep Sleep Mode ofCPU operation. The use of the DACOUT voltage as the reference makes the Deep Sleep offset afixed percentage of the VID setting, as required by specifications.Battery Optimized Mode (BOM) Shift. This is an analog I/O pin whose output is the VID referencevoltage and whose input current is programmed by an external resistance to ground. The current isused in the IC to set a switched bias current out of the RAMP pin, depending on whether it isactivated by the BOM signal. When activated, this added bias current creates a downward shiftof the regulated core voltage to a predetermined optimum level for regulation corresponding toBattery Optimized Mode of CPU operation. The use of the DACOUT voltage as the referencemakes the DSHIFT a fixed percentage of the VID setting, as required by specifications.26REG27CS+28CS–29HYSSET30DSHIFT31BSHIFT–8–REV. 0

ADP3204

PIN FUNCTION DESCRIPTIONS (continued)Pin32MnemonicDPRSHIFTFunctionDeeper Sleep Shift. This is an analog I/O pin whose output is a fixed voltage reference and whoseinput current is programmed by an external resistor to ground. The current is used to set twoswitched bias currents that flow into both the REG and COREFB pins, depending on the DPRSLPsignal. When activated, the REG pin bias current creates an upward shift of the regulated corevoltage from the internally set (default) Deeper Sleep value to the voltage level specified by the CPUDeeper Sleep operation. The COREFB bias current creates the same amount of downward shift ofthe COREFB voltage is. The shifted back COREFB voltage compared against the internally setDeeper Sleep voltage to create Power Good information. Use of the Deeper Sleep Shift adjustmentand the DACRAMP rate control features are exclusive.V_5SD3BAR43SV_DCC433.3␮FC330.1␮FR1062.7⍀ADP3415C321␮F2x0.1␮FC37 . . . C404x10␮F1INV_3SR42.7⍀C20.1µFRHYSSET21.5k⍀ 1%RDSHIFT8.87k⍀ 1%RBSHIFT21.5k⍀ 1%RDPRSHIFTOPTIONAL: DEEPERSLEEPVOLTAGE ADJUSTMENT10pFBST10DRVH9SW8Q5IR7811WQ6IR7811WL30.32␮HD6MBRS130LT3RCS33m⍀R1510⍀C310.018␮FQ13IR7822Q14IR78222SD3DRVLSDC11µFR180 ⍀RC 1.5k⍀ 1%4DLY5VCCGND7DRVL6RCL 576 1%RA243 1%C3C410pFRB 54.9k⍀V_5SCOC4700pFC423.3␮FC230.1␮FR1022.7⍀D2BAR43SV_DCDPRSHIFT32DSHIFT30BSHIFT31HYSSET29CS–28CS+27REG26RAMP25C321␮F2x0.1␮FVR_ VID4VR_ VID3VR_ VID2 VR_ VID11234VID4VID3VID2VID1VID0BOMDPSLPVCCCS32423222120191817RDR91.05k⍀1%1.05k⍀1%C61000pFC910pFR170 ⍀1IN2SDADP3415BST10DRVH9SWGNDDRVL876Q3IR7811WQ4IR7811WC27 . . . C304x10␮FADP3204CS2CS1OUT3OUT2OUT115DACRAMP3DRVLSD4DLY5VCCL20.32␮HRCS23m⍀16DACOUT14COREFB12DRVLSD5 VR_ VID0220k⍀6GMUXSEL(IMVP-II ONLY)7STP_CPU8DPRSLPVRR14D5MBRS130LT310⍀C210.018␮FQ12IR7822DPRSLP9PWRGD11CLAMPGNDQ11IR7822V_5SD1BAR43S10SDV_3S3k⍀VR_PWRGDCORE_ON13SSC413.3␮FC130.1␮FR1042.7⍀BST10DRVH9SW8GNDDRVL76V_DCC121␮F2x0.1␮FC17 . . . C204x10␮FADP34151CSS0.047␮FR90300k⍀23D90JP1SET: LATCHED OCPOPEN: HICCUP OCPV5R205.1k⍀4R160⍀5INSDDRVLSDDLYVCCQ1IR7811WQ2IR7811WL10.32␮HRCS13m⍀R23D4MBRS130LT310⍀C110.018␮FVCC COREQ7IR7807VC44...C496x220␮FVCC-VID (1.2V)BAR43SQ9IR7822Q10IR7822Figure 1.Typical ApplicationREV. 0–9–

ADP3204–Typical Performance Characteristics

10000NORMAL OPERATING MODE A␮ –1000 TNUVLO MODEERRUC LYPP100USSHUTDOWN MODE10020406080100AMBIENT TEMPERATURE – ؇CTPC 1.Supply Current vs. Temperature1.77+1%1.76V – TUPTU1.75FULL SCALEO CAD1.741.73؊1%020406080100AMBIENT TEMPERATURE – CTPC 2.DAC Output Voltage vs. Temperature0.6200.6150.610+8.5mV V– 0.605TUTPZERO SCALE VID [11111]U0.600O CAD0.595؊8.5mV0.5900.5850.580020406080100AMBIENT TEMPERATURE – CTPC 3.DAC Output Voltage vs. TemperatureHIGHDGRWPLOW؊0.15؊0.1؊0.0500.050.10.15RELATIVE CORE VOLTAGE – %TPC 4.Power Good vs. Relative Core Voltage Variation10s1m – MEIT TR0.1AT STFOS0.010.0010.1110100SOFT START CAPACITANCE – nFTPC 5.Soft Start Timing vs. Timing Capacitor110.0108.0% –106.0 EMIT104.0 GNIK102.0NAL100.0B DE98.0ZILA96.0MRON94.092.090.0020406080100AMBIENT TEMPERATURE – CTPC 6.PWRGD Blanking Time vs. TemperatureNormalized to 25°C–10–REV. 0

ADP3204

110ICS – CURRENT LIMIT THRESHOLD – ␮A0OUT = HIGH, RHYS = 17k⍀HYSTERESIS CURRENT – ␮A–50–100–150–200OUT = LOW, RHYSSET = 170k⍀OUT = HIGH, RHYSSET = 170k⍀OUT = HIGH, RHYS = 170k⍀0OUT = LOW, RHYS = 170k⍀OUT = LOW, RHYSSET = 17k⍀–250–300OUT = HIGH, RHYSSET = 17k⍀–350020406080100OUT = LOW, RHYS = 17k⍀–110020406080100TEMPERATURE – ؇CAMBIENT TEMPERATURE – ؇CTPC 7.Core Hysteresis Current vs. TemperatureTPC 8.Current Limit Threshold vs. TemperatureTHEORY OF OPERATIONOverviewFeedback/Current SensingFeaturing a new proprietary 1-, 2-, or 3-channel buck converterhysteretic control architecture developed by Analog Devices, theADP3204 is the optimal core voltage control solution for bothIMVP-II and IMVP-III generation microprocessors. The complexmultitiered regulation requirements of either IMVP specifica-tion are easily implemented with the highly integrated function-ality of this controller.Power Conversion Control ArchitectureAccurate current sensing is needed to accomplish output voltagepositioning accurately, which, in turn, is required to allow theminimum number of output capacitors to be used to containtransients. A current sense resistor is used between each inductorand the output capacitors. To allow the control to operatewithout amplifiers, the negative feedback signal is multiplexedfrom the inductor or upstream side of the current sense resistors,and a positive feedback signal, if needed for load-line tuning, istaken from the output or downstream side.Output Voltage Programming by VID, Offsets, and Load LineDriving of the individual channels is accomplished using externaldrivers, such as the ADP3415. One PWM interface pin perchannel, OUT1, OUT2, and OUT3, is provided. A separatepin, DRVLSD, commands the driver to enable or disable synchro-nous rectifier operation during the off time of each channel. Thesame DRVLSD pin is connected to all three drivers.The ADP3204 utilizes hysteretic control. The resistor fromthe HYSSET pin to ground sets up a current that is switchedbidirectionally into a resistor interconnected between the RAMPand CS+ pins. The switching of this current sets the hysteresis.In a multichannel configuration, the hysteretic control requiresmultiplexing information in all channels. The inductor currentof the channel that is driven high is controlled against the upperhysteresis limit. During the common offtime of the channels,the inductor currents are averaged together and compared againstthe lower hysteresis limit. This proprietary offtime averagingtechnique serves to eliminate a systematic offset that otherwiseappears in a fully multiplexed hysteretic control system.CompensationIn the IMVP-II and IMVP-III specifications, the output voltageis a function of both the core current (according to a specifiedload line) and the system operating mode (i.e., performance orbattery optimized, normal or deep sleep clocking state, or deepersleep). The VID code programs the “nominal” core voltage.The core voltage decreases as a function of load current alongthe load line, which is synonymous with an output resistance ofthe power converter. The core voltage is also offset by a dcvalue—usually specified as a percentage—depending on theoperating mode. The voltage offset is also called a “shift.”Two pins, BSHIFT and DSHIFT, are used to program themagnitude of the voltage shifts. The voltage shifts are accom-plished by injecting current at the node of the negative input pinof the feedback comparator. Resistive termination at the pinsdetermines the magnitude of the voltage “shifts.”Two other pins, BOM and DPSLP, are used to activate therespective two shifts only in their active low states. In theADP3204, the shifts are mutually exclusive, with the DeepSleep shift (controlled by the DPSLP and DSHIFT pins) beingthe dominant one. Another pin, DPRSLP, eliminates bothshifts only in its active high state. Its assertion corresponds tothe Deeper Sleep operating mode.Current LimitingAs with all ADI products for core voltage control, the controlleris compatible with ADOPT compensation, which provides theoptimum output voltage containment within a specified voltagewindow or along a specified load line using the fewest possibleoutput capacitors. The inductor ripple current is kept at a fixedprogrammable value while the output voltage is regulated withfully programmable voltage positioning parameters, which canbe tuned to optimize the design for any particular CPU regula-tion specification. By controlling the ripple current rather thanthe ripple voltage, the frequency variations associated withchanges in output impedance for standard ripple regulators willnot appear.REV. 0

The current programmed at the HYSSET pin and a resistorfrom the CS– pin to the common node of the current senseresistors set the current limit. If the current limit threshold istriggered, a hysteresis is applied to the threshold so that hystereticcontrol is maintained during a current limited operating mode.–11–

ADP3204

SoftStart and HiccupA capacitor from the SS pin to ground determines both the softstart time and the frequency at which hiccup will occur under acontinuous short circuit or overload.System Signal InterfaceSeveral pins of the ADP3204 are meant to connect directly tosystem signals. The VID pins connect to the system VIDcontrol signals. The DPRSLP pin connects to the system’sDPRSLPVR signal. The DPSLP pin connects to the system’sDPSLP or STPCPU signal. The BOM signal connects to thesystem’s GMUXSEL signal. In an IMVP-II system, theGMUXSEL signal precedes any VID code change with a fewnanoseconds, while in an IMVP-III system, it follows it with amaximum 12 µs delay. To comply with both specifications, theADP3204 has a VID register in front of the DAC inputs that iswritten by a short pulse generated at the rising or falling edge ofthe GMUXSEL signal. In an IMVP-II configuration, if theexternal VID multiplex settling time is longer than the internalVID register’s write pulsewidth, then the insertion of an externalRC delay network in the GMUXSEL signal path (in front of theBOM pin) is recommended. The Intel specification calls formaximum 200 ns VID code setup time. This specification canbe met with a simple RC network that consists of only a 220 kΩresistor and no external capacitor, just the BOM pin’s capacitance.Undervoltage Lockoutconfiguration, the latched off state of the system would beindicative of a system failure. The overvoltage/reverse voltageprotective means is via not allowing the continued application ofenergy to the CPU core. The design objective should be, however,to ensure that the CPU core could safely absorb the remainingenergy in the power converter, since this energy is not clampedas in the preferred configuration.LAYOUT CONSIDERATIONSAdvantages in PCB LayoutAnalog Devices provides ADP3204/3415 as a dedicated three-phase power management solution for IMVP-III Intel P4mobile core supply.This three-phase solution separates the controller (ADP3204)and the MOSFET drivers (ADP3415). Today, most motherboardsonly leave small pieces of PCB area for the power managementcircuit. Therefore, the separation of the controller and theMOSFET drivers gives much greater freedom in layout thanany single chip solution.Meanwhile, the separation also provides the freedom to placethe analog controller in a relatively quiet area in the motherboard.This can minimize the susceptibility of the controller to injectednoise. Any single chip solution with a high speed loop designwill suffer larger susceptibility to jitter that appears as modulationof the output voltage.The ADP3204 maximizes the integration of IMVP-III features.Therefore, no additional externally implemented functions arerequired to comply with IMVP-III specifications. This savesPCB area for component placement on the motherboard.PCB Layout Consideration for ADP3204/3415The ADP3204’s supply pin, VCC, has undervoltage lockout(UVLO) functionality to ensure that if the supply voltage is toolow to maintain proper operation, the IC will remain off and ina low current state.Overvoltage Protection (OVP) and Reverse VoltageProtection (RVP)The ADP3204 features a comprehensive redundantly monitoredOVP and RVP implementation to protect the CPU core againstan excessive or reverse voltage, e.g., as might be induced by acomponent or connection failure in the control or power stage.Two pins are associated with the OVP/RVP circuitry—a pin foroutput voltage feedback, COREFB, which is also used forpower good monitoring but not for voltage regulation, and anoutput pin, CLAMP.The CLAMP pin defaults to a low state at startup of theADP3204 and remains low until an overvoltage or reversevoltage condition is detected. If either condition is detected, theCLAMP signal is asserted and latched high.For maximum and fastest protection, the CLAMP pin shouldbe used to drive the gate of a power MOSFET whose drainsource is connected across the CPU core voltage. Detection ofovervoltage or reverse voltage will clamp the core voltage toessentially zero, thus quickly removing the fault condition andpreventing further energy from being applied to the CPU core.For a less comprehensively protective and less costly solution,the CLAMP pin may be used to latch the disconnection ofinput power. The latch should be powered whenever any inputpower source is present. Typically, such a latching circuit isalready present in a system design, so it becomes only a matterof allowing the CLAMP pin to also trigger the latch. In thisThe following guidelines are recommended for optimal perfor-mance of the ADP3204 and ADP3415 in a power converter.The circuitry is considered in three parts: the power switchingcircuitry, the output filter, and the control circuitry.Placement Overview1.For ideal component placement, the output filter capacitorswill divide the power switching circuitry from the controlsection. As an approximate guideline considered on a single-sided PCB, the best layout would have components alignedin the following order: ADP3415, MOSFETs and inputcapacitor, output inductor, current sense resistor, outputcapacitors, control components, and ADP3204. Note thatthe ADP3204 and ADP3415 are completely separated for anideal layout, which is impossible with a single-chip solution.This keeps the noisy switched power section isolated fromthe precision control section and gives more freedom in thelayout of the power switching circuitry.2.Whenever a power dissipating component (e.g., a powerMOSFET) is soldered to a PCB, the liberal use of vias, bothdirectly on the mounting pad if possible and immediatelysurrounding it, is recommended. Two important reasons forthis are: improvement of the current rating through the vias(if it is a current path) and improved thermal performance,especially if there is opportunity to spread the heat with aplane on the opposite side of the PCB.–12–REV. 0

ADP3204

Power Switching CircuitryADP3415, MOSFETs, and Input Capacitors

Control CircuitryADP3204, Control Components

3.Locate the ADP3415 near the MOSFETs so that the loopinductance in the path of the top gate drive returned to theSW pin is small, and similarly for the bottom gate drivewhose return path is the ground plane. The GND pinshould have at least one very close via into the ground plane.Locate the input bypass MLC capacitors close to the MOSFETsso that the physical area of the loop enclosed in the electricalpath through the bypass capacitor and around through thetop and bottom MOSFETs (drain-source) is small and wide.This is the switching power path loop.Make provisions for thermal management of all the MOSFETs.Heavy copper and wide traces to ground and power planeswill help to pull the heat out. Heat sinking by a metal tapsoldered in the power plane near the MOSFETs will help.Even just a small airflow can help tremendously. ParalleledMOSFETs to achieve a given resistance will help spread the heat.An external Schottky diode (across the bottom MOSFET)may increase efficiency by a small amount (< ~1%), depend-ing on its forward voltage drop compared to the MOSFET’sbody diode at a given current; a MOSFET with a built-inSchottky is more effective. For an external Schottky, it shouldbe placed next to the bottom MOSFET or it may not beeffective at all.The VCC bypass capacitor should be close to the VCC pinand connected on either a very short trace to the GND pinor to the GND plane.12.If the ADP3204 cannot be placed as previously recom-mended, care should be taken to keep the device andsurrounding components away from radiation sources(e.g., from power inductors) and capacitive coupling fromnoisy power nodes.13.Noise immunity can be improved by the use of a devotedsignal ground plane for the power controller and itssurrounding components. Space for a ground plane mightreadily be available on a signal plane of the PCB since it isoften unused in the vicinity of the power controller.14.If critical signal lines (i.e., signals from the current senseresistor leading back to the ADP3204) must cross throughpower circuitry, it is best if a signal ground plane can beinterposed between those signal lines and the traces of thepower circuitry. This serves as a shield to minimize noiseinjection into the signals.15.Absolutely avoid crossing any signal lines over the switchingpower path loop, described previously.16.Accurate voltage positioning depends on accurate currentsensing, so the control signals that monitor the voltagedifferentially across the current sense resistor should beKelvin-connected. Please refer to ADI Evaluation Board ofthe ADP3204 and its documentation for control signalconnection with sense resistors.17.The RC filter used for the current sense signal should belocated near the control components as this serves thedual purpose of filtering out the effect of the current senseresistors’ parasitic inductance and the noise picked up alongthe routing of the signal. The former purpose is achieved byhaving the time constant of the RC filters approximatelymatched to that of the sense resistors, and is importantfor maintaining the accuracy of the current signal.APPLICATION INFORMATIONTheoretical Background4.5.6. 7.Output FilterOutput Inductor and Capacitors, Current Sense Resistor

8.9.Locate the current sense resistors very near to the outputvoltage plane.The load-side heads of sense resistors should join as closelyas possible for accurate current signal measurement ofeach phase.10.PCB trace resistances from the current sense resistors tothe regulation point should be minimized, known (calcu-lated or measured), and compensated for as part of thedesign if it is significant. (Remote sensing is not sufficientfor relieving this requirement.) A square section of 1-ouncecopper trace has a resistance of ~0.5 mΩ, which adds tothe specified DC output resistance of the power converter.The output capacitors should similarly be close to theregulation point and well tied into power planes as imped-ance here will add to the “AC output resistance” (i.e., theESR) that is implicitly specified as well.11.Whenever high currents must be routed between PCBlayers, vias should be used liberally to create parallel currentpaths so that the resistance and inductance are minimizedand the via current rating is not exceeded.This application section presents the theoretical background formultiphase dc-to-dc converters using the ADP320x family ofcontrollers for mobile CPUs. Members of that family controlmultiphase ripple regulators (also called hysteretic regulators) ina configuration that allows employing ADOPT, Analog Devices’optimal voltage positioning technique to implement the desiredoutput voltage and load line, both statically and dynamically, asrequired by Intel’s IMVP-II and IMVP-III specifications.Single-Phase Hysteretic Regulator with ADOPT

Figure 2 shows the conventional single-phase hystereticregulator and the characteristic waveforms. The operation is asfollows. During the time the upper transistor, Q1, is turned on,the inductor current, IL, and also the output voltage, VOUT,increase. When VOUT reaches the upper threshold of thehysteretic comparator, Q1 is turned off, Q2 is turned on, andthe inductor current and the output voltage decrease. The cyclerepeats after VOUT reaches the lower threshold of the hystereticcomparator.REV. 0–13–

ADP3204

VINVOUTVHQ1VSWQ2LILCORE+LOADVOUTVSWandCOCCR=OERCSRD2(2)

t From (Equation 2), the series resistance is:tVHVREFRCS= ILtRER1+DRC(3)

Figure 2.Conventional Hysteretic Regulator andIts Characteristic WaveformsThis is the ADOPT configuration and design procedure thatallows the maximum possible ESR to be used while meeting agiven load-line specification.It can be seen from Equation 3 that unless RD is zero or RC isinfinite, RCS will always be smaller than RE. An advantage ofthe circuit in Figure 3 is that if we select the ratio RD/RC wellabove unity, the additional dissipation introduced by the seriesresistance RCS will be negligible. Another interesting feature ofthe circuit in Figure 3 is that the ac voltage across the twoinputs of the hysteretic comparator is now equal only to the acvoltage across RCS. This is due to the presence of the capacitorCOC, which effectively couples the ac component of the outputvoltage to the noninverting input voltage of the comparator.Since the comparator sees only the ac voltage across RCS, in thecircuit in Figure 3 the dependence of the switching frequencyon the ESR of the output capacitor is completely eliminated.Equation 4 presents the expression for the switching frequency.f=

RCS (VIN−VOUT)

VOUT

LVHVIN

(4)

Since there is no voltage error amplifier in the hystereticregulator, its response to any change in the load current or theinput voltage is virtually instantaneous. Therefore, the hystereticregulator represents the fastest possible dc-to-dc converter. Aslight disadvantage of the conventional hysteretic regulator isthat its frequency varies with the input and output voltages. In atypical mobile CPU converter application, the worst-casefrequency variation due to the input voltage variation is in theorder of 30%, which is usually acceptable. In the simplestimplementation of the hysteretic converter, shown in Figure 2,the frequency also varies proportionally with the ESR, RE, of theoutput capacitor. Since the initial value is often poorly con-trolled, and the ESR of electrolytic capacitors also changes withtemperature and age, practical ESR variations can easily lead toa frequency variation in the order of three to one. However, amodification of the hysteretic topology eliminates the depen-dence of the operating frequency on the ESR. In addition, themodification allows the optimal implementation, ADOPT, ofIntel’s IMVP-II and IMVP-III load-line specifications. Figure 3shows the modified hysteretic regulator.VINMultiphase Hysteretic Regulator with ADOPT

Q1VSWQ2LILCOCRCSCORCRDRE+VOUTVHVREFFigure 3.Modified Hysteretic Regulator with ADOPTThe implementation requires adding a resistive divider (RCand RD) between the reference voltage and the output, andconnecting the tap of the divider to the noninverting inputof the hysteretic comparator. A capacitor, COC, is placedacross the upper member (RC) of the divider.

It is easily shown that the output impedance of the con-verter can be no less than the ESR of the output capacitor.A straightforward derivation demonstrates that the outputimpedance of the converter in Figure 3 can be minimized toequal the ESR, RE, when the following two equations arevalid (neglecting PCB trace resistance for now):

Multiphase converters have very important advantages, includ-ing reduced rms current in the input filter capacitor (allowingthe use of a smaller and less expensive device), distributed heatdissipation (reducing the hot spot temperature and increasingreliability), higher total power capability, increased equivalentfrequency without increased switching losses (allowing the useof smaller equivalent inductances, and thereby shortening theload transient time), and reduced ripple current in the outputcapacitor (reducing the output ripple voltage and allowing theuse of a smaller and less expensive output capacitor). Also, theyhave some disadvantages, which should be considered whenchoosing the number of phases. Those disadvantages include theneed for more switches and output inductors than in a single-phasedesign (leading to higher cost than a single-phase solution, atleast below a certain power level), more complex control, andthe possibility of uneven current sharing among the phases.The family of ADP320x controllers alleviates two of the abovedisadvantages of multiphase converters. It presents a simple andcost-effective control solution, and provides perfect currentsharing among the phases. Figure 4 shows a simplified blockdiagram of a three-phase converter using the control principleimplemented with the ADP3204, the three-phase member ofthe ADP320x family.As Figure 4 shows, in the multiphase configuration, the ripplecurrent signal is multiplexed from all channels. During the ontime of any given channel, its current is compared to the upperthreshold of the hysteretic comparator. When the currentreaches the upper threshold, the control FET of that channel isREV. 0

RER=1+DRCSRC (1)

–14–

ADP3204

turned off. During the common off time of all channels, theircurrents are averaged and compared to the lower threshold.When the averaged channel current reaches the lower threshold,the hysteretic comparator changes state again, and turns on thecontrol FET of the next channel, as selected by the phasesplitter logic. This control concept ensures that the peakcurrents of all channels will be the same, and therefore thechannel currents will be perfectly balanced. The ADOPTcompensation can be used the same way as in the single-phaseversion discussed previously.Since due to second-order effects, the detailed design of amultiphase converter with the ADP320x family is rathercomplex, a design aid using MathSoft’s MathCAD™ programhas been developed. Please contact ADI for further information.PHASE 1L1IL1VINRCS1VOUTPHASE 2L2IL2RCS2RECOLOADPHASE 3L3IL3RCS3PHASESPLITTEROUT 3OUT 2OUT 1HYSTERETICCORECOMPARATORCURRENTSENSE MUXCS1CS2CS3COCRCRDVREFFigure 4.3-Phase Modified Hysteretic Regulator with ADOPTMathCAD is a trademark of MathSoft.REV. 0–15–

ADP3204

OUTLINE DIMENSIONS32-Lead Frame Chip Scale Package [LFCSP](CP-32)Dimensions shown in millimeters5.000.60 MAXBSC SQ0.60 MAXPIN 1INDICATOR25PIN 124321INDICATOR0.50TOP4.75BSC3.25VIEWBSC SQBOTTOMVIEW3.10SQ2.950.500.40171680.30912؇ MAX0.70 MAX3.500.65 NOMREF0.05 MAX1.000.02 NOM0.900.300.80SEATING0.230.25 REFCOPLANARITYPLANE0.180.08COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2–16–)0(20/11–0–14820C.A.S.U NI DETNIRPREV. 0