High CMR, High SpeedOptocouplersTechnical Data
HCPL-4504HCPL-0454HCNW4504
Features
• Short Propagation Delaysfor TTL and IPMApplications
• 15 kV/µs Minimum CommonMode Transient Immunity atVCM = 1500 V for TTL/LoadDrive
• High CTR at TA = 25°C>25% for HCPL-4504/0454>23% for HCNW4504
• Electrical Specifications forCommon IPM Applications• TTL Compatible
• Guaranteed Performancefrom 0°C to 70°C
• Open Collector Output• Safety Approval
UL Recognized - 2500 V rmsfor 1 minute (5000 V rms for1 minute for
HCPL-4504#020 andHCNW4504)per UL1577CSA Approved
VDE 0884 Approved-VIORM = 630 V peak forHCPL-4504#060
-VIORM = 1414 V peak forHCNW4504
BSI Certified (HCNW4504)• Available in 8-Pin DIP, SO-8,Widebody Packages
Applications
• Inverter Circuits and
Intelligent Power Module(IPM) interfacing -High Common Mode TransientImmunity (> 10 kV/µs for anIPM load/drive) and (tPLH - tPHL)Specified (See Power InverterDead Time section)• Line Receivers -Short Propagation Delays andLow Input-Output Capacitance• High Speed Logic GroundIsolation - TTL/TTL, TTL/CMOS, TTL/LSTTL• Replaces PulseTransformers-Save Board Space and Weight• Analog Signal GroundIsolation -Integrated PhotodetectorProvides Improved Linearityover Phototransistors
Description
These optocouplers are similar toHP’s other high speed transistoroptocouplers but with shorterpropagation delays and higherCTR. The HCPL-4504/0454 andHCNW4504 also have a guaran-teed propagation delay difference(tPLH - tPHL). These features makethese optocouplers an excellentsolution to IPM inverter dead timeand other switching problems.
Functional Diagram
NC1ANODE2CATHODE3NC48VCC7NC6VO5GNDTRUTH TABLELEDVOONLOWOFFHIGHA 0.1 µF bypass capacitor between pins 5 and 8 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
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5965-3604E
The HCPL-4504/0454 andHCNW4504 CTR, propagationdelay, and CMR are specified forboth TTL and IPM load/driveconditions. Specifications andtypical performance plots for bothTTL and IPM conditions areprovided for ease of application.
These single channel, diode-transistor optocouplers are
available in 8-Pin DIP, SO-8, andWidebody package configura-tions. An insulating layer betweena LED and an integrated
photodetector provide electricalinsulation between input andoutput. Separate connections for
the photodiode bias and output-transistor collector increase thespeed up to a hundred times thatof a conventional phototransistorcoupler by reducing the basecollector capacitance.
Selection Guide
Single Channel Packages
8-Pin DIP(300 Mil)HCPL-4504
Small Outline
SO-8HCPL-0454
Widebody(400 Mil)HCNW4504
Ordering Information
Specify Part Number followed by Option Number (if desired).Example:HCPL-4504#XXX020 = UL 5000 V rms/1 Minute Option*
060 = VDE 0884 VIORM = 630 V peak Option*300 = Gull Wing Surface Mount Option†500 = Tape and Reel Packaging Option
Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor forinformation.
*For HCPL-4504 only. Combination of Option 020 and Option 060 is not available.†Gull wing surface mount option applies to through hole parts only.
Schematic
ICC8VCCANODE+2VFIFCATHODE–3SHIELDIO6VO5GND1-34
Package Outline Drawings
8-Pin DIP Package (HCPL-4504)
9.65 ± 0.257.62 ± 0.25(0.380 ± 0.010)(0.300 ± 0.010)TYPE NUMBER8765OPTION CODE*6.35 ± 0.25(0.250 ± 0.010)HP XXXXZDATE CODEYYWWUL1234RECOGNITION1.19 (0.047) MAX.1.78 (0.070) MAX.5° TYP.0.254+ 0.076- 0.051
4.70 (0.185) MAX.(0.010+ 0.003)- 0.002)
0.51 (0.020) MIN.2.92 (0.115) MIN.DIMENSIONS IN MILLIMETERS AND (INCHES).
1.080 ± 0.3200.65 (0.025) MAX.* MARKING CODE LETTER FOR OPTION NUMBERS.(0.043 ± 0.013)RU2.54 ± 0.25\"L\" = OPTION 020(0.100 ± 0.010)\"V\" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
8-Pin DIP Package with Gull Wing Surface Mount Option 300 (HCPL-4504)
PAD LOCATION (FOR REFERENCE ONLY)9.65 ± 0.25(0.380 ± 0.010)1.016 (0.040)1.194 (0.047)8765(0.190)4.826TYP.6.350 ± 0.25(0.250 ± 0.010)9.398 (0.370)9.906 (0.390)12340.381 (0.015)1.194 (0.047)0.635 (0.025)1.778 (0.070)1.7809.65 ± 0.25(0.070)(0.380 ± 0.010)1.19MAX.(0.047)7.62 ± 0.25MAX.(0.300 ± 0.010)0.254+ 0.076- 0.051(0.165)4.19MAX.(0.010+ 0.003)- 0.002)1.080 ± 0.320(0.043 ± 0.013)0.635 ± 0.25(0.025 ± 0.010)2.540.635 ± 0.13012° NOM.(0.100)(0.025 ± 0.005)BSCDIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES).1-35
Small Outline SO-8 Package (HCPL-0454)
87653.937 ± 0.127(0.155 ± 0.005)XXXYWW5.842 ± 0.203(0.236 ± 0.008)TYPE NUMBER(LAST 3 DIGITS)DATE CODE12340.381 ± 0.076(0.016 ± 0.003)1.270BSG(0.050)5.080 ± 0.127(0.200 ± 0.005)7°0.432(0.017)45° X3.175 ± 0.127(0.125 ± 0.005)1.524(0.060)0.152 ± 0.051(0.006 ± 0.002)0.228 ± 0.025(0.009 ± 0.001)DIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES).0.305MIN.(0.012)8-Pin Widebody DIP Package (HCNW4504)
11.15 ± 0.15(0.442 ± 0.006)876511.00MAX.(0.433)9.00 ± 0.15(0.354 ± 0.006)TYPE NUMBERDATE CODEHP HCNWXXXXYYWW12341.55(0.061)MAX.10.16 (0.400)TYP.7° TYP.+ 0.0760.254- 0.0051+ 0.003)(0.010- 0.002)5.10MAX.(0.201)3.10 (0.122)3.90 (0.154)2.54 (0.100)TYP.1.78 ± 0.15(0.070 ± 0.006)0.40 (0.016)0.56 (0.022)0.51 (0.021) MIN.DIMENSIONS IN MILLIMETERS (INCHES).1-36
8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300 (HCNW4504)
11.15 ± 0.15(0.442 ± 0.006)PAD LOCATION (FOR REFERENCE ONLY)8765(0.242)6.15TYP.9.00 ± 0.15(0.354 ± 0.006)12.30 ± 0.30(0.484 ± 0.012)12341.30.9(0.051)(0.035)1.5512.30 ± 0.30(0.061)(0.484 ± 0.012)MAX.11.00(0.433)MAX.(0.158)4.00MAX.1.78 ± 0.15(0.070 ± 0.006)1.00 ± 0.152.540.75 ± 0.25(0.039 ± 0.006)(0.100)(0.030 ± 0.010)0.254+ 0.076- 0.0051BSC(0.010+ 0.003)- 0.002)DIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES).7° NOM.Solder Reflow Temperature Profile
(HCPL-0454 and Gull Wing Surface Mount Option Parts)
260240220∆T = 145°C, 1°C/SEC200∆T = 115°C, 0.3°C/SECC°180 – E160RU140TA120RE100PM80ET60∆T = 100°C, 1.5°C/SEC4020001234567101112TIME – MINUTESNote: Use of nonchlorine activated fluxes is highly recommended.
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Regulatory Information
The devices contained in this datasheet have been approved by thefollowing organizations:UL
Recognized under UL 1577,Component RecognitionProgram, File E55361.
CSA
Approved under CSA ComponentAcceptance Notice #5, File CA88324.
VDE
Approved according to VDE0884/06.92 (HCNW4504 andHCPL-4504#060 only).
BSI
Certification according toBS451:1994,
(BS EN60065:1994);BS EN60950:1992(BS7002:1992) and
EN41003:1993 for Class II
applications (HCNW4504 only).
Insulation and Safety Related Specifications
ParameterMinimum ExternalAir Gap (ExternalClearance)Minimum ExternalTracking (ExternalCreepage)
Minimum InternalPlastic Gap
(Internal Clearance)
SymbolL(101)
8-Pin DIP (300 Mil)Value
7.1
SO-8Value4.9
Widebody(400 Mil)ValueUnits
9.6
mm
Conditions
Measured from input terminals
to output terminals, shortestdistance through air.
Measured from input terminalsto output terminals, shortestdistance path along body.Through insulation distance,conductor to conductor, usuallythe direct distance between thephotoemitter and photodetectorinside the optocoupler cavity.Measured from input terminalsto output terminals, alonginternal cavity.
DIN IEC 112/VDE 0303 Part 1
L(102)7.44.810.0mm
0.080.081.0mm
Minimum InternalTracking (InternalCreepage)
Tracking Resistance(ComparativeTracking Index)Isolation Group
CTI
NANA4.0mm
200200200Volts
IIIaIIIaIIIa
Material Group
(DIN VDE 0110, 1/, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
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VDE 0884 Insulation Related Characteristics(HCPL-4504 OPTION 060 ONLY)
DescriptionInstallation classification per DIN VDE 0110/1., Table 1for rated mains voltage ≤300 V rmsfor rated mains voltage ≤450 V rmsClimatic ClassificationPollution Degree (DIN VDE 0110/1.)Maximum Working Insulation VoltageInput to Output Test Voltage, Method b*VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,Partial Discharge < 5 pCInput to Output Test Voltage, Method a*VIORM x 1.5 = VPR, Type and sample test,tm = 60 sec, Partial Discharge < 5 pCHighest Allowable Overvoltage*(Transient Overvoltage, tini = 10 sec)Safety Limiting Values(Maximum values allowed in the event of a failure,also see Figure 15, Thermal Derating curve.)Case TemperatureInput CurrentOutput PowerInsulation Resistance at TS, VIO = 500 VSymbolCharacteristic I-IVI-III55/100/2126301181UnitsVIORMVPRVPRVIOTMV peakV peak945V peak6000V peakIS,INPUTPS,OUTPUTRSTS175230600≥109°CmAmWΩVDE 0884 Insulation Related Characteristics (HCNW4504 ONLY)
DescriptionInstallation classification per DIN VDE 0110/1., Table 1for rated mains voltage ≤600 V rmsfor rated mains voltage ≤1000 V rmsClimatic ClassificationPollution Degree (DIN VDE 0110/1.)Maximum Working Insulation VoltageInput to Output Test Voltage, Method b*VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,Partial Discharge < 5 pCInput to Output Test Voltage, Method a*VIORM x 1.5 = VPR, Type and sample test,tm = 60 sec, Partial Discharge < 5 pCHighest Allowable Overvoltage*(Transient Overvoltage, tini = 10 sec)Safety Limiting Values(Maximum values allowed in the event of a failure,also see Figure 15, Thermal Derating curve.)Case TemperatureInput CurrentOutput PowerInsulation Resistance at TS, VIO = 500 VSymbolCharacteristic I-IVI-III55/85/21214142652UnitsVIORMVPRVPRVIOTMV peakV peak2121V peak8000V peakIS,INPUTPS,OUTPUTRSTS150400700≥ 109°CmAmWΩ*Refer to the front of the optocoupler section of the current catalog under Product Safety Regulations section (VDE 0884), for adetailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits inapplication.
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Absolute Maximum RatingsParameterStorage TemperatureOperating TemperatureSymbolTSTAMin.-55HCPL-4504-55HCPL-0454HCNW4504-55HCPL-4504HCPL-0454HCNW4504HCPL-4504HCPL-0454HCNW4504HCPL-4504HCPL-0454HCNW4504HCPL-4504HCPL-0454HCNW4504DeviceMax.1251008525504010.15345408163020100Units°C°CNoteAverage Forward Input CurrentPeak Forward Input Current(50% duty cycle, 1 ms pulse width)(50% duty cycle, 1 ms pulse width)Peak Transient Input Current(≤1 µs pulse width, 300 pps)Reverse LED Input Voltage (Pin 3-2)IF(AVG)IF(PEAK)mAmAA12IF(TRANS)VRVInput Power DissipationPINmW3Average Output Current (Pin 6)Peak Output CurrentSupply Voltage (Pin 8-5)Output Voltage (Pin 6-5)Output Power DissipationLead Solder Temperature(Through-Hole Parts Only)1.6 mm below seating plane,10 seconds up to seating plane, 10 secondsReflow Temperature ProfileIO(AVG)IO(PEAK)VCCVOPO-0.5-0.5mAmAVVmW4TLSTRPHCPL-4504 HCNW4504HCPL-0454andOption 300260°C260°CSee Package OutlineDrawings section1-40
Electrical Specifications (DC)
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified. See note 12.
ParameterCurrent
Transfer Ratio
SymbolCTR
Device Min.HCPL-450425HCPL-045421HCNW450423
19HCPL-450426HCPL-045422HCNW45042521HCPL-4504HCPL-0454HCNW4504
Typ.*32342931353733350.20.20.0030.01500.02
HCPL-4504HCPL-0454HCNW4504HCPL-4504HCPL-0454HCNW4504HCPL-4504HCPL-0454HCNW4504HCPL-4504HCPL-0454HCNW4504
1.5
1.451.3553
-1.6-1.460701.59
Max.6060636565680.40.50.40.50.5150200121.71.81.851.95
Units Test Conditions%TA = 25°CVO = 0.4 VIF = 16 mA,
VO = 0.5 VVCC = 4.5 V
TA = 25°CVO = 0.4 V
VO = 0.5 V%TA = 25°CVO = 0.4 VIF = 12 mA,
VO = 0.5 VVCC = 4.5 V
TA = 25°CVO = 0.4 V
VO = 0.5 VVTA = 25°CIO = 4.0 mAIF = 16 mA,
VCC = 4.5 VIO = 3.3 mATA = 25°CIO = 3.6 mA
IO = 3.0 mAµATA = 25°CVO = VCC = 5.5 VIF = 0 mA
TA = 25°CVO = VCC = 15 VµAµAV
IF = 16 mA, VO = Open, VCC = 15 VTA = 25°CIF = 0 mA, VO = Open,
VCC = 15 V
TA = 25°CIF = 16 mATA = 25°CIF = 16 mAV
IR = 10 µA
Fig.1, 2,4
Note5
Current
Transfer Ratio
CTR
1, 2,4
5
Logic Low
Output Voltage
VOL
Logic HighOutput CurrentLogic Low
Supply CurrentLogic HighSupply CurrentInput ForwardVoltage
IOH
5
ICCLICCHVF
1212
3
Input ReverseBreakdownVoltage
TemperatureCoefficient ofForward VoltageInput
Capacitance
BVR
∆VF∆TACIN
IR = 100 µA, TA = 25°C
mV/°CIF = 16 mA
pF
f = 1 MHz, VF = 0 V
*All typicals at TA = 25°C.
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AC Switching Specifications
ParameterPropagationDelay Timeto Logic Lowat OutputSymboltPHL0.20.5 Min.Typ.0.2
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified.
Max.Units0.3µs TA = 25°CTest ConditionsPulse: f = 20 kHz,Duty Cycle = 10%,IF = 16 mA, VCC = 5.0 V,RL = 1.9 kΩ, CL = 15 pF,VTHHL = 1.5 VPulse: f = 10 kHz,Duty Cycle = 50%,IF = 12 mA, VCC = 15.0 V,RL = 20 kΩ, CL = 100 pF,VTHHL = 1.5 VPulse: f = 20 kHz,Duty Cycle = 10%,IF = 16 mA, VCC = 5.0 V,RL = 1.9 kΩ, CL = 15 pF,VTHLH = 1.5 VPulse: f = 10 kHz,Duty Cycle = 50%,IF = 12 mA, VCC = 15.0 V,RL = 20 kΩ, CL = 100 pF,VTHLH = 2.0 VFig.6,8, 9Note90.20.10.50.50.71.0TA = 25°C6,10-1410PropagationDelay Timeto LogicHigh atOutput0.3tPLH0.30.5µs0.7TA = 25°C6,8, 990.30.20.80.81.11.4TA = 25°C6,10-1410PropagationDelayDifferenceBetweenAny 2 PartsCommonModeTransientImmunity atLogic HighLevel Output CommonModeTransientImmunity at Logic LowLevel Output-0.4tPLH-tPHL-0.70.30.30.9µs1.3TA = 25°CPulse: f = 10 kHz,6,Duty Cycle = 50%,10-14IF = 12 mA, VCC = 15.0 V,RL = 20 kΩ, CL = 100 pF,VTHHL = 1.5 V, VTHLH = 2.0 VVCC = 5.0 V, RL = 1.9 kΩ,CL = 15 pF, IF = 0 mA71515|CMH|1530kV/µs30VCM=1500 VP-PTA = 25°C7, 9VCC = 15.0 V, RL = 20 kΩ,CL = 100 pF, IF = 0 mAVCC = 5.0 V, RL = 1.9 kΩ,CL = 15 pF, IF = 16 mA78, 1015|CML|1030kV/µs30VCM=1500 VP-PTA = 25°C77, 9VCC = 15.0 V, RL = 20 kΩ,CL = 100 pF, IF = 12 mAVCC = 15.0 V, RL = 20 kΩ,CL = 100 pF, IF = 16 mA78, 1015*All typicals at TA = 25°C.
30778, 108, 101-42
Package Characteristics
Over recommended temperature (TA = 0°C to 25°C) unless otherwise specified.ParameterInput-OutputMomentaryWithstandVoltage†Input-OutputResistanceSym.VISODeviceMin.HCPL-45042500HCPL-0454 HCNW4504 5000HCPL-4504(Option 020)HCPL-4504HCPL-0454HCNW4504HCPL-4504HCPL-0454HCNW4504500010121012101110130.60.50.6pFΩVI-O = 500 VdcTA = 25°CTA = 100°Cf = 1 MHzTyp.*Max. Units Test ConditionsV rmsRH ≤50%,t = 1 min.,TA = 25°CFig.Note6, 136, 14 6, 11,146RI-OInput-OutputCapacitanceCI-O6*All typicals at TA = 25°C..
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-outputcontinuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (ifapplicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output EnduranceVoltage.”
Notes:
1.Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C (8-Pin DIP).Derate linearly above 85°C free-air temperature at a rate of 0.5 mA/°C (SO-8).
2.Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C (8-Pin DIP).Derate linearly above 85°C free-air temperature at a rate of 1.0 mA/°C (SO-8).
3.Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C (8-Pin DIP).Derate linearly above 85°C free-air temperature at a rate of 1.1 mW/°C (SO-8).
4.Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C (8-Pin DIP).Derate linearly above 85°C free-air temperature at a rate of 2.3 mW/°C (SO-8).
5.CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current, IO, to the forward LED input current,IF, times 100.
6.Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
7.Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive)dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state
(i.e.,VO>2.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on thetrailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V).8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level isthe maximum tolerable dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in aLogic High state (i.e., VO > 3.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt onthe trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a Logic Low state(i.e.,VO<1.0V).
9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.10. The RL = 20 kΩ, CL = 100 pF load represents an IPM (Intelligent Power Module) load.11. See Option 020 data sheet for more information.
12. Use of a 0.1 µF bypass capacitor connected between pins 5 and 8 is recommended.
13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥3000 V rms for 1 second
(leakage detection current limit, Ii-o ≤5 µA). This test is performed before the 100% Production test shown in the VDE 0884Insulation Related Characteristics Table, if applicable.
14. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 V rms for 1 second
(leakage detection current limit, Ii-o ≤5 µA). This test is performed before the 100% Production test shown in the VDE 0884Insulation Related Characteristics Table, if applicable.
15. The difference between tPLH and tPHL between any two devices (same part number) under the same test condition. (See Power
Inverter Dead Time and Propagation Delay Specifications section.)
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HCPL-4504/0454T = 25°CA10V = 5.0 VCCIO – OUTPUT CURRENT – mAHCNW450440 mAIO – OUTPUT CURRENT – mA35 mA30 mA25 mAT = 25°CA20V = 5.0 VCC181614121082040 mA35 mA30 mA25 mA20 mA15 mA10 mAI = 5 mAF520 mA15 mA10 mA0I = 5 mAF010VO – OUTPUT VOLTAGE – V20010VO – OUTPUT VOLTAGE – V20Figure 1. DC and Pulsed Transfer Characteristics.
NORMALIZED CURRENT TRANSFER RATIO1.5NORMALIZED CURRENT TRANSFER RATIOHCPL-4504/0454HCNW45042.01.61.20.80.40NORMALIZEDIF = 16 mAVO = 0.4 V = 5.0 VVCCTA = 25°C1.00.50.0NORMALIZEDIF = 16 mAVO = 0.4 V = 5.0 VVCCTA = 25°C02468101214161820222426 IF – INPUT CURRENT – mA0510152025 IF – INPUT CURRENT – mAFigure 2. Current Transfer Ratio vs. Input Current.
HCPL-4504/04541000IF – FORWARD CURRENT – mAIF – FORWARD CURRENT – mAHCNW45041000T = 25°CA100101.00.10.010.0011.2 IF+VF–100101.00.10.010.0011.1 IF+VF–T = 25°CA1.21.31.41.51.61.31.41.51.61.7VF – FORWARD VOLTAGE – VOLTSVF – FORWARD VOLTAGE – VOLTSFigure 3. Input Current vs. Forward Voltage.
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NORMALIZED CURRENT TRANSFER RATIONORMALIZED CURRENT TRANSFER RATIOIOH – LOGIC HIGH OUTPUT CURRENT – nAHCPL-4504/04541.11.0HCNW45041.05NORMALIZEDIF = 16 mA = 0.4 VVOVCC = 5.0 VTA = 25°C10410310210110010-110-2-60-40-201.0IF = 0 mAVO = VCC = 5.0 V0.9NORMALIZEDIF = 16 mAVO = 0.4 VVCC = 5.0 VTA = 25°C0.950.80.70.90.6-60-40-200204060801001200.85-60-40-20020406080100120020406080100120 TA – TEMPERATURE – °C TA – TEMPERATURE – °C TA – TEMPERATURE – °CFigure 4. Current Transfer Ratio vs. Temperature.
Figure 5. Logic High Output Currentvs. Temperature.
IF0VOVTHHLVCCPULSEGEN.Z = 50ΩOt = 5 nsrIF1238760.1µF5RLVCCVTHLHVOLI MONITORFRMVO4C LtPHLtPLHFigure 6. Switching Test Circuit.
VCM0 Vtr10%190%90%10%tfBAIF234VFFVOLVCM+–PULSE GEN.8760.1µF5RLVCCVOVOSWITCH AT A: I = 0 mAFVOSWITCH AT B: I = 12 mA, 16 mAFVCCCLFigure 7. Test Circuit for Transient Immunity and Typical Waveforms.
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HCPL-4504/0454 HCNW45040.50V0.50sCC = 5.0 VVsCC = 5.0 Vµ0.45R L = 1.9 kΩµ0.45R L = 1.9 kΩ–– Y0.40CL = 15 pFVYALTHHL = VTHLH = 1.5 VtA0.40CL = 15 pFtEPLHVLTHHL = VTHLH = 1.5 VPLH0.3510% DUTY CYCLEED D 0.3510% DUTY CYCLENON0.30tPHLOIIT0.30ATtGA0.25GPHLA0.25PAPO0.20OR0.20PRP –0.15IF = 10 mA–I I F = 10 mApF = 16 mAp0.15ttIF = 16 mA0.10-60-40-200204060801001200.10-60-40-20020406080100120 TA – TEMPERATURE – °C TA – TEMPERATURE – °CFigure 8. Propagation Delay Time vs. Temperature.
2.61.12.4VVsCC = 5.0 VsCC = 15.0 VIF = 10 mAµ2.2Tµ1.0R A = 25° C L = 20 kΩIF = 16 mA–– Y2.0CL = 100 pFYAV0.9CL = 100 pFVL1.8THHL = 1.5 VATHHL = 1.5 V V1.6THLH = 2.0 VLtEEPLHD 50% DUTY CYCLED 0.8VTHLH = 2.0 VN50% DUTY CYCLEO1.4tNPLHOIIT0.7A1.2TGAA1.0GPIF = 10 mA0.6O0.8AtPRPHLIF = 16 mA0.5P0.6OR t–PHL 0.4P – p0.4t0.2pt0.0024681012141618200.3-60-40-20020406080100120 RL– LOAD RESISTANCE – kΩ TA – TEMPERATURE – °CFigure 10. Propagation Delay Time vs.Figure 11. Propagation Delay Time vs.Load Resistance.Temperature.3.5V1.2sCC = 15.0 VtµPLHs –3.0TA = 25° Cµ1.1TA = 25° CRΩ L = 20 k YRL = 20 kΩ– Y1.0CL = 100 pFAL2.5VTHHL = 1.5 VAVTHHL = 1.5 VEVDTHLH = 2.0 VL0.9EVDTHLH = 2.0 V N2.050% DUTY CYCLE N0.850% DUTY CYCLEOItPHLOITT0.7tPLHA1.5AGG0.6AAP1.0POO0.5RRPP 0.5IF = 10 mA 0.4tPHL–I– ptpt0.3IF = 16 mAF = 10 mAIF = 16 mA0.0010020030040050060070080090010000.21011121314151617181920 RL – LOAD CAPACITANCE – pF VCC – SUPPLY VOLTAGE – VFigure 13. Propagation Delay Time vs.Figure 14. Propagation Delay Time vs.Load Capacitance.Supply Voltage.
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1.4VsCC = 5.0 Vµ –1.2TA = 25° C YCL = 15 pFAVL1.0THHL = VTHLH = 1.5 VE10% DUTY CYCLED N0.8tPLHOITAG0.6APO0.4 tIPHL F = 10 mAIRF = 16 mAP – 0.2pt0.002468101214161820 RL – LOAD RESISTANCE – kΩFigure 9. Propagation Delay Time vs.Load Resistance.
1.8V = 15.0 Vs1.6CCµT A = 25° C– Y1.4CL = 100 pFAVLTHHL = 1.5 VED1.2VTHLH = 2.0 Vt PLHNO1.050% DUTY CYCLEITA0.8GtAP0.6PHLORP0.4 – pt0.2IF = 10 mAI0.0F = 16 mA05101520253035404550 RL – LOAD RESISTANCE – kΩFigure 12. Propagation Delay Time vs.Load Resistance.
SI HCPL-4504 OPTION 060– 800TNPS (mW)ER700IRS (mA)UC600 TUP500NI ,S400P – R300EW(230)O200P T100UPT0UO0255075100125150175200TS – CASE TEMPERATURE – °CSI – 1000HCNW4504TN (mW)E900PSRIRS (mA)U800C T700UPN600I ,S500P –400 REW300OP200 TU100PT0UO0255075100125150175TS – CASE TEMPERATURE – °CFigure 15. Thermal Derating Curve,Dependence of Safety Limiting Valvewith Case Temperature per VDE 0884.
Power Inverter DeadTime and PropagationDelay Specifications
The HCPL-4504/0454 and
HCNW4504 include a specifica-tion intended to help designersminimize “dead time” in theirpower inverter designs. The new“propagation delay difference”specification (tPLH-tPHL) is usefulfor determining not only how
much optocoupler switching delayis needed to prevent “shoot-through” current, but also fordetermining the best achievableworst-case dead time for a givendesign.
When inverter power transistorsswitch (Q1 and Q2 in Figure 17),it is essential that they never
+HV+HCPL-4504/0454HCNW45048LED 1276BASE/GATE3OUT 1DRIVE CIRCUITQ15+HCPL-4504/0454HCNW45048LED 2276BASE/GATE3OUT 2DRIVE CIRCUITQ25Figure 16. Typical Power Inverter.
–HVLED 1OUT 1tPLH min(tPLH max–tPLH min)tPLH maxTURN-ON DELAY(tPLH max–tPLH min)LED 2OUT 2tPHL min(tPHL max–tPHL min)tPHL maxMAXIMUM DEAD TIMEFigure 17. LED Delay and Dead Time Diagram.
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conduct at the same time.
Extremely large currents will flowif there is any overlap in theirconduction during switchingtransitions, potentially damagingthe transistors and even the sur-rounding circuitry. This “shoot-through” current is eliminated bydelaying the turn-on of onetransistor (Q2) long enough toensure that the opposing
transistor (Q1) has completelyturned off. This delay introduces asmall amount of “dead time” atthe output of the inverter duringwhich both transistors are offduring switching transitions.Minimizing this dead time is animportant design goal for aninverter designer.
The amount of turn-on delayneeded depends on the propaga-tion delay characteristics of theoptocoupler, as well as thecharacteristics of the transistorbase/gate drive circuit. Consider-ing only the delay characteristicsof the optocoupler (the charac-teristics of the base/gate drivecircuit can be analyzed in thesame way), it is important to
know the minimum and maximumturn-on (tPHL) and turn-off (tPLH)propagation delay specifications,preferably over the desired
operating temperature range. Theimportance of these specificationsis illustrated in Figure 17. Thewaveforms labeled “LED1”,
“LED2”, “OUT1”, and “OUT2” arethe input and output voltages ofthe optocoupler circuits drivingQ1 and Q2 respectively. Mostinverters are designed such thatthe power transistor turns onwhen the optocoupler LED turnson; this ensures that both powertransistors will be off in the eventof a power loss in the controlcircuit. Inverters can also bedesigned such that the power
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transistor turns off when theoptocoupler LED turns on; thistype of design, however, requiresadditional fail-safe circuitry toturn off the power transistor if anover-current condition is
detected. The timing illustrated inFigure 17 assumes that the powertransistor turns on when theoptocoupler LED turns on.The LED signal to turn on Q2should be delayed enough so thatan optocoupler with the veryfastest turn-on propagation delay(tPHLmin) will never turn on beforean optocoupler with the very
slowest turn-off propagation delay(tPLHmax) turns off. To ensure this,the turn-on of the optocouplershould be delayed by an amountno less than (tPLHmax-tPHLmin),which also happens to be the
maximum data sheet value for thepropagation delay differencespecification, (tPLH-tPHL). TheHCPL-4504/0454 and
HCNW4504 specify a maximum(tPLH-tPHL) of 1.3 µs over anoperating temperature rangeof0-70°C.
Although (tPLH-tPHL)max tells thedesigner how much delay is
needed to prevent shoot-throughcurrent, it is insufficient to tell thedesigner how much dead time adesign will have. Assuming thatthe optocoupler turn-on delay isexactly equal to (tPLH - tPHL)the minimum dead time is zeromax,(i.e., there is zero time betweenthe turn-off of the very slowestoptocoupler and the turn-on ofthe very fastest optocoupler).Calculating the maximum deadtime is slightly more complicated.Assuming that the LED turn-ondelay is still exactly equal to(tPLH-tPHL)max, it can be seen inFigure 17 that the maximum dead
time is the sum of the maximumdifference in turn-on delay plusthe maximum difference in turn-off delay,
[(tPLHmax-tPLHmin)+(tPHLmax-tPHLmin)].This expression can berearranged to obtain
[(tPLHmax-tPHLmin)-(tPHLmin-tPHLmax)],and further rearranged to obtain[(tPLH-tPHL)max-(tPLH-tPHL)min],which is the maximum minus theminimum data sheet values of(tPLH-tPHL). The differencebetween the maximum and
minimum values depends directlyon the total spread in propagationdelays and sets the limit on howgood the worst-case dead timecan be for a given design.
Therefore, optocouplers with tightpropagation delay specifications(and not just shorter delays orlower pulse-width distortion) canachieve short dead times in powerinverters. The HCPL-4504/0454and HCNW4504 specify a
minimum (tPLH-tPHL) of -0.7 µsover an operating temperaturerange of 0-70°C, resulting in amaximum dead time of 2.0 µswhen the LED turn-on delay isequal to (tPLH-tPHL)max, or 1.3µs.It is important to maintainaccurate LED turn-on delaysbecause delays shorter than
(tPLH-tPHL)max may allow shoot-through currents, while longerdelays will increase the worst-casedead time.
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