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M37906F8CSP资料

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

DESCRIPTION

These are single-chip 16-bit microcomputers designed with high-per-formance CMOS silicon gate technology, including the internal flashmemory and being packaged in 42-pin plastic molded SSOP orshrink plastic molded DIP. These microcomputers support the 7900Series instruction set, which are enhanced and expanded instructionset and are upper-compatible with the 7700/7751 Series instructionset.

The CPU of these microcomputers is a 16-bit parallel processor thatcan also be switched to perform 8-bit parallel processing. Also, thebus interface unit of these microcomputers enhances the memoryaccess efficiency to execute instructions fast. Therefore, these mi-crocomputers are suitable for office, business, and industrial equip-ment controller that require high-speed processing of large data.Also, they are suitable for motor-control equipment since each ofthem includes the motor control circuit.

For the internal flash memory, single-power-supply programmingand erasure, using a PROM programmer or the control by the cen-tral processing unit (CPU), is supported. Also, each of these micro-computers has the memory area dedicated for storing a certainsoftware which controls programming and erasure (reprogrammingcontrol software). Therefore, on these microcomputers, the programcan easily be changed even after they are mounted on the board.

Power supply voltage..................................................5 V ± 0.5 VProgramming/Erase voltage........................................5 V ± 0.5 VProgramming method....................Programming in a unit of wordErase method............................................Block erase or Total eraseM37906F8CFP, M37906F8CSP

...............4 blocks (8 Kbytes ✕ 2, 16 Kbytes ✕ 1, 28 Kbytes ✕ 1)Programming/Erase control by software command

Maximum number of reprograms............................................100

••••••

APPLICATION

• Control devices for office equipment such as copiers and facsimiles• Control devices for industrial equipment such as communication•

and measuring instruments

Control devices for equipment, requiring motor control, such asinverter air conditioners and general-purpose inverters

DISTINCTIVE FEATURES

Number of basic machine instructions....................................203Memory

Flash memory (User ROM area)...................................60 KbytesRAM.............................................................................3072 bytesFlash memory (Boot ROM area).....................................8 KbytesInstruction execution time

The fastest instruction at 20 MHz frequency........................50 nsSingle power supply....................................................5 V ± 0.5 VInterrupts...........5 external sources, 21 internal sources, 7 levelsMulti-functional 16-bit timer.................................................10 + 3(Three-phase motor drive waveform or Pulse motor drive waveformoutput is available.)

Serial I/O (UART or Clock synchronous).....................................210-bit A-D converter............................................5-channel inputs8-bit D-A converter............................................2-channel outputs12-bit watchdog timer

Programmable input/output (ports P1, P2, P5, P6, P7).............30

•••••••••••

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

M37906F8CFP PIN CONFIGURATION (TOP VIEW)VREFAVSS(Note)P74/AN4/DA1/INT3/RTPTRG0P73/AN3/DA0P72/AN2P71/AN1P70/AN0P65/TA2IN/U/RTP11P/TA2OUT/V/RTP10P63/TA1IN/W/RTP03P62/TA1OUT/U/RTP02P61/TA0IN/V/RTP01P60/TA0OUT/W/RTP00P57/INT7/TB2IN/IDUP56/INT6/TB1IN/IDV(Note)P55/INT5/TB0IN/IDWP6OUTCUT/INT4MD0VCONTRESETVCC1234567101112131415161718192021424140393837363534333231302928272625242322AVCCP10/CTS0/RTS0P11/CTS0/CLK0P12/RxD0P13/TxD0P14/CTS1/RTS1P15/CTS1/CLK1P16/RxD1P17/TxD1P20/TA4OUTP21/TA4INP22/TA9OUTP23/TA9INP24(/TB0IN)P25(/TB1IN)P26(/TB2IN)P27(/INT3/RTPTRG0)MD1XOUTXINVSSOutline 42P2R-EM37906F8CFP(Note)Note: Allocation of pins TB0IN to TB2INand INT3/RTPTRG0 can be switch-ed by software.2

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

M37906F8CSP PIN CONFIGURATION (TOP VIEW)VREFAVSS(Note)P74/AN4/DA1/INT3/RTPTRG0P73/AN3/DA0P72/AN2P71/AN1P70/AN0P65/TA2IN/U/RTP11P/TA2OUT/V/RTP10P63/TA1IN/W/RTP03P62/TA1OUT/U/RTP02P61/TA0IN/V/RTP01P60/TA0OUT/W/RTP00P57/INT7/TB2IN/IDUP56/INT6/TB1IN/IDV(Note)P55/INT5/TB0IN/IDWP6OUTCUT/INT4MD0VCONTRESETVCC1234567101112131415161718192021424140393837363534333231302928272625242322AVCCP10/CTS0/RTS0P11/CTS0/CLK0P12/RxD0P13/TxD0P14/CTS1/RTS1P15/CTS1/CLK1P16/RxD1P17/TxD1P20/TA4OUTP21/TA4INP22/TA9OUTP23/TA9INP24(/TB0IN)P25(/TB1IN)P26(/TB2IN)P27(/INT3/RTPTRG0)MD1XOUTXINVSSOutline 42P4BM37906F8CSP(Note)Note: Allocation of pins TB0IN to TB2INand INT3/RTPTRG0 can be switch-ed by software.3

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

Data Bus (Even)Data Bus (Odd)Data Buffer DQ0 (8)Data Buffer DQ1 (8)Data Buffer DQ2 (8)Address BusData Buffer DQ3 (8)P6OUTCUTInstruction Queue Buffer Q0 (8)Instruction Queue Buffer Q1 (8)Instruction Queue Buffer Q2 (8)Reference Voltage InputInstruction Queue Buffer Q3 (8)VREFInstruction Queue Buffer Q4 (8)D-A1 Converter (8)Instruction Queue Buffer Q5 (8)Instruction Queue Buffer Q6 (8)Instruction Register (8)AVccInstruction Queue Buffer Q7 (8)Instruction Queue Buffer Q8 (8)Instruction Queue Buffer Q9 (8)(0V)AVSSBusInterfaceUnit(BIU)Watchdog TimerTimer TB2 (16)Program Address Register PA (24)MD1Data Address Register DA (24)Timer TB0 (16)Timer TB1 (16)UART0 (9)UART1 (9)Incrementer (24)A-D Converter (10)D-A0 Converter (8)Incrementer/Decrementer (24)MD0Program Counter PC (16)Program Bank Register PG (8)Timer TA9 (16)Timer TA6 (16)Timer TA8 (16)Timer TA7 (16)(0V)VssInput Buffer Register IB (16)P2(8)Data bank Register DT (8)Timer TA5 (16)Timer TA3 (16)Timer TA1 (16)Timer TA4 (16)Timer TA2 (16)Processor Status Register PS (11)Timer TA0 (16)VccDirect Page Register DPR0 (16)Direct Page Register DPR1 (16)Direct Page Register DPR2 (16)RAM3072 bytesReset inputRESETDirect Page Register DPR3 (16)Central Processing Unit (CPU)Stack Pointer S (16)Index Register Y (16)Clock outputFlash Memory60 KbytesXOUTClock Generating CircuitIndex Register X (16)Accumulator B (16)Accumulator A (16)BLOCK DIAGRAMClock inputXIN4

VCONTArithmetic LogicUnit (16)Input/Output port P7P7(5)Input/Output port P6P6(6)Input/Output port P5P5(3)Input/Output port P2Input/Output port P1P1(8)元器件交易网www.cecb2b.com

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

FUNCTIONS (Microcomputer mode)

Parameter

Number of basic machine instructionsInstruction execution time

External clock input frequency f(XIN)System clock input frequency f(fsys)Memory size

Flash memory (User ROM area)RAM

Flash memory (Boot ROM area)

Programmable input/outputports

P1, P2P5P6P7

Multi-functional timers

TA0–TA9TB0–TB2

Serial I/OA-D converterD-A converterDead-time timerWatchdog timerInterrupts

Maskable interrupsNon-maskable interrups

Clock generating circuitPLL frequency multiplierPower supply voltagePower dissipationPorts’ input/outputcharacteristics

Input/Output withstand voltageOutput currentUART0 and UART1

Functions

203

50 ns (the fastest instruction at f(fsys) = 20 MHz)20 MHz (Max.)20 MHz (Max.)60 Kbytes3072 bytes8 Kbytes8-bit ✕ 23-bit ✕ 16-bit ✕ 15-bit ✕ 116-bit ✕ 1016-bit ✕ 3

(UART or Clock synchronous serial I/O) ✕ 2

10-bit successive approximation method ✕ 1 (5 channels)8-bit ✕ 28-bit ✕ 312-bit ✕ 1

5 external sources, 18 internal sources. Each interrupt can be setto a priority level within the range of 0–7 by software.3 internal sources

Incorporated (externally connected to a ceramic resonator orquartz-crystal resonator).

The following multiplication ratios are available: ✕ 2, ✕ 3, ✕ 45 V±0.5 V

125 mW (at f(fsys) = 20 MHz, Typ.; the PLL frequency multiplier is inactive.)5 V5 mA

Not available (single-chip mode only).–20 to 85 °C

CMOS high-performance silicon gate process(Note)

Memory expansion

Operating ambient temperature rangeDevice structurePackage

Note:

PackagesM37906F8CFPM37906F8CSP

42-pin plastic molded SSOP (42P2R-E)42-pin shrink plastic molded DIP (42P4B)

5

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

FUNCTIONS (Flash memory mode)

Parameter

Power supply voltageProgramming/Erase voltageFlash memory modeBlock division for erasure

User ROM areaBoot ROM area

Programming method

Flash memory parallel I/O modeFlash memory serial I/O modeFlash memory CPU reprogramming modeErase method

Flash memory parallel I/O modeFlash memory serial I/O modeFlash memory CPU reprogramming modeProgramming/Erase controlNumber of commands

Maximum number of reprograms

5 V±0.5 V5 V±0.5 V

3 modes: parallel I/O, serial I/O, and CPU reprogramming modes4 blocks (8 Kbytes ✕ 2, 16 Kbytes ✕ 1, 28 Kbytes ✕ 1); total of

60 Kbytes

1 block (8 Kbytes ✕ 1) (Note)Programmed per word

User ROM area + Boot ROM areaUser ROM areaUser ROM areaTotal erase/Block erase

User ROM area + Boot ROM areaUser ROM areaUser ROM area

Programming/Erase control by software commands6 commands100

Functions

Note: On shipment, our reprogramming control firmware for the flash memory serial I/O mode has been stored into the boot ROM area.

6

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

PIN DESCRIPTION (MICROCOMPUTER MODE)

PinVcc, VssMD0MD1RESETXINXOUTVCONTAVcc,

AVssVREFP10–P17

Name

Power supply inputMD0MD1Reset inputClock inputClock output

Filter circuit connectionAnalog power supply inputReference voltage inputI/O port P1

Input/Output—InputInputInputInputOutput——InputI/O

Connect this pin to VSS.Connect this pin to Vss.

The microcomputer is reset when “L” level is applied to this pin.

These are input and output pins of the internal clock generating circuit. Connect aceramic or quartz-crystal oscillator between the XIN and XOUT pins. When anexternal clock is used, the clock source should be connected to the XIN pin, and theXOUT pin should be left open.

When using the PLL frequency multiplier, connect this pin to the filter circuit. Whennot using the PLL frequency multiplier, this pin should be left open.

Power supply input pins for the A-D converter and the D-A converter. Connect AVccto Vcc, and AVss to Vss externally.

This is the reference voltage input pin for the A-D converter and the D-A converter.Port P1 is an 8-bit I/O port. This port has an I/O direction register, and each pincan be programmed for input or output. These pins enter the input modeat reset. These pins also function as I/O port pins of UART0 and UART1.

In addition to having the same functions as port P1, these pins also function as I/Opins for timers A4 and A9. By software setting, these pins also function as inputpins for timers B0–B2, an input pin for INT3, and a trigger input pin in the pulseoutput port mode.

In addition to having the same functions as port P1, these pins also function asinput pins for INT5–INT7, input pins for timers B0–B2, and input pins for position-data-input pins in the three-phase waveform mode.

In addition to having the same functions as port P1, these pins also function as I/Opins for timers A0–A2, and output pins for the motor drive waveform.

In addition to having the same functions as port P1, these pins also function asinput pins for the A-D converter. P73 functions as an output pin for the D-A

converter; P74 functions as an output pin for the D-A converter, an input pin forINT3, and a trigger input pin in the pulse output port mode.

This pin has the function to forcibly place port P6 pins in the input mode. Also, thispin functions as an input pin for INT4; and this pin is used to input a signal, whichforcibly cuts off a motor drive waveform output.

Functions

Apply 5 V±0.5 V to Vcc, and 0 V to Vss.

P20–P27I/O port P2I/O

P50–P57I/O port P5I/O

P60–P65P70–P74

I/O port P6I/O port P7

I/OI/O

P6OUTCUTP6OUTCUT inputInput

7

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

PIN DESCRIPTION (FLASH MEMORY SERIAL I/O MODE)

PinVCC, VSSMD0MD1XINXOUTAVcc, AVssVREFRESET

_____Name

Power supply inputMD0MD1Reset inputClock inputClock outputAnalog supply inputReference voltage input

Input/Output—InputInputInputInputOutput—InputInputInputInputI/OOutputInputInputInputInput—

Connect this pin to Vss.

Functions

Apply 5 V ± 0.5 V to Vcc, and 0 V to Vss.

Connect this pin to Vss via a resistor of 10 kΩ to 100 kΩ.The reset input pin.

Connect a ceramic oscillator between the XIN and XOUT pins, or input an externalclock from the XIN pin with the XOUT pin left open.Connect AVcc to Vcc, and AVss to Vss.

Input an arbitrary level within the range of VSS–VCC. (This is not used in the flash memory serial I/O mode.)Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)This is an input pin for a serial clock.

This is an I/O pin for serial data. Connect this pin to VCC via a resistor (about 1 kΩ).This is an output pin for the BUSY signal.Input “H”.

Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)Connect this pin to the filter circuit, or leave this pin open. (This is not used in the flashmemory serial I/O mode.)Input port P1P10–P17

P20–P23, P27Input port P2P24P25P26

P6OUTCUTP55–P57P60–P65P70–P74VCONT

SCLK inputSDA I/OBUSY outputP6OUTCUT inputInput port P5Input port P6Input port P7

Filter circuit connection

8

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

BASIC FUNCTION BLOCKS

Each of the M37906F8CFP and M37906F8CSP has the same func-tion as that of the M37906M4C-XXXFP except for the following.

Therefore, for details except for the following, refer to the datasheetof the M37906M4C-XXXFP.• Flash memory size• RAM size

MEMORY

Figure 1 shows the memory map.

00000016000000160000FF16000100160003FF1600040016Peripheral devices’ control registersUnused area00000016Peripheral devices’ control registers(See Figures 2 and 3.)0000FF16Bank 016Internal RAM3072 bytes000FFF160010001600FFFF1600FFB416Internal ROM60 KbytesInterrupt vector tableReserved areaReserved areaTimer A9Timer A8Timer A7Timer A6Timer A5INT7INT6INT5Reserved areaAddress matching detect00FFB41600FFFF16Reserved areaReserved areaINT4INT3A-D conversionUART1 transmitUART1 receiveUART0 transmitUART0 receiveTimer B2Timer B1Timer B0Timer A4Timer A3Timer A2Timer A1Timer A0Reserved areaReserved areaReserved areaReserved areaWatchdog timerDBCBRK instructionZero divideRESET00FFFE16Fig. 1 Memory map of M37906F8CFP, M37906F8CSP (Single-chip mode)

9

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

Address (Hexadecimal notation)00000016Reserved area (Note)00000116Reserved area (Note)00000216Reserved area (Note)00000316Port P1 register00000416Reserved area (Note)00000516Port P1 direction register00000616Port P2 register00000716Reserved area (Note)00000816Port P2 direction register00000916Reserved area (Note)00000A16Reserved area (Note)00000B16Port P5 register00000C16Reserved area (Note)00000D16Port P5 direction register00000E16Port P6 register00000F16Port P7 register00001016Port P6 direction register00001116Port P7 direction register00001216Reserved area (Note)0000131600001416Reserved area (Note)0000151600001616Reserved area (Note)00001716Reserved area (Note)00001816Reserved area (Note)00001916Reserved area (Note)00001A1600001B1600001C1600001D1600001E16A-D control register 000001F16A-D control register 100002016A-D register 00000211600002216A-D register 10000231600002416A-D register 20000251600002616A-D register 30000271600002816A-D register 40000291600002A16Reserved area (Note)00002B16Reserved area (Note)00002C16Reserved area (Note)00002D16Reserved area (Note)00002E16Reserved area (Note)00002F16Reserved area (Note)00003016UART0 transmit/receive mode register00003116UART0 baud rate register (BRG0)00003216UART0 transmit buffer register 0000331600003416UART0 transmit/receive control register 000003516UART0 transmit/receive control register 100003616UART0 receive buffer register 0000371600003816UART1 transmit/receive mode register00003916UART1 baud rate register (BRG1)00003A16UART1 transmit buffer register 00003B1600003C16UART1 transmit/receive control register 000003D16UART1 transmit/receive control register 100003E16UART1 receive buffer register 00003F16Address (Hexadecimal notation)00004016Count start register 000004116Count start register 100004216One-shot start register 000004316One-shot start register 100004416Up-down register 000004516Timer A clock division select register00004616Timer A0 register0000471600004816Timer A1 register0000491600004A16Timer A2 register00004B1600004C16Timer A3 register00004D1600004E16Timer A4 register00004F1600005016Timer B0 register0000511600005216Timer B1 register0000531600005416Timer B2 register0000551600005616Timer A0 mode register00005716Timer A1 mode register00005816Timer A2 mode register00005916Timer A3 mode register00005A16Timer A4 mode register00005B16Timer B0 mode register00005C16Timer B1 mode register00005D16Timer B2 mode register00005E16Processor mode register 000005F16Processor mode register 100006016Watchdog timer register00006116Watchdog timer frequency select register00006216Particular function select register 000006316Particular function select register 1000016Particular function select register 200006516Reserved area (Note)00006616Debug control register 000006716Debug control register 10000681600006916Address comparison register 000006A1600006B1600006C16Address comparison register 100006D1600006E16INT3 interrupt control register00006F16INT4 interrupt control register00007016A-D conversion interrupt control register00007116UART0 transmit interrupt control register00007216UART0 receive interrupt control register00007316UART1 transmit interrupt control register00007416UART1 receive interrupt control register00007516Timer A0 interrupt control register00007616Timer A1 interrupt control register00007716Timer A2 interrupt control register00007816Timer A3 interrupt control register00007916Timer A4 interrupt control register00007A16Timer B0 interrupt control register00007B16Timer B1 interrupt control register00007C16Timer B2 interrupt control register00007D16Reserved area (Note)00007E16Reserved area (Note)00007F16Reserved area (Note)Note: Do not write to this address.Fig. 2 Location of SFRs (1)

10

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

Address (Hexadecimal notation)00008016

000081160000821600008316000084160000851600008616000087160000881600001600008A1600008B1600008C1600008D1600008E1600008F160000901600009116000092160000931600009416000095160000961600009716000098160000991600009A1600009B1600009C1600009D1600009E1600009F160000A0160000A1160000A2160000A3160000A4160000A5160000A6160000A7160000A8160000A9160000AA160000AB160000AC160000AD160000AE160000AF160000B0160000B1160000B2160000B3160000B4160000B5160000B6160000B7160000B8160000B9160000BA160000BB160000BC160000BD160000BE160000BF16

Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)

Address (Hexadecimal notation)0000C0160000C1160000C2160000C3160000C4160000C5160000C6160000C7160000C8160000C9160000CA160000CB160000CC160000CD160000CE160000CF160000D0160000D1160000D2160000D3160000D4160000D5160000D6160000D7160000D8160000D9160000DA160000DB160000DC160000DD160000DE160000DF160000E0160000E1160000E2160000E3160000E4160000E5160000E6160000E7160000E8160000E9160000EA160000EB160000EC160000ED160000EE160000EF160000F0160000F1160000F2160000F3160000F4160000F5160000F6160000F7160000F8160000F9160000FA160000FB160000FC160000FD160000FE160000FF16

Up-down register 1Timer A5 registerTimer A6 registerTimer A7 registerTimer A8 registerTimer A9 registerTimer A01 registerTimer A11 registerTimer A21 register

Timer A5 mode registerTimer A6 mode registerTimer A7 mode registerTimer A8 mode registerTimer A9 mode registerReserved area (Note)Comparator function select register 0Reserved area (Note)Comparator result register 0Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)

Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)

External interrupt input read-out registerD-A control registerD-A register 0D-A register 1

Reserved area (Note)Reserved area (Note)Flash memory control registerReserved area (Note)Reserved area (Note)Reserved area (Note)

Waveform output mode registerDead-time timer

Three-phase output data register 0Three-phase output data register 1

Position-data-retain function control registerSerial I/O pin control registerPort P2 pin function control registerReserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Reserved area (Note)Clock control register 0Reserved area (Note)Reserved area (Note)Reserved area (Note)

Timer A5 interrupt control registerTimer A6 interrupt control registerTimer A7 interrupt control registerTimer A8 interrupt control registerTimer A9 interrupt control register

INT5 interrupt control registerINT6 interrupt control registerINT7 interrupt control registerNote: Do not write to this address.

Fig. 3 Location of SFRs (2)

11

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

FLASH MEMORY MODEThese microcomputers contain the flash memory; and single-power-supply reprogramming is available to this. These microcomputershave the following three modes, enabling reading/programming/era-sure for the flash memory:• Flash memory parallel I/O mode and Flash memory serial I/Omode, where the flash memory is handled by using an external pro-grammer.• CPU reprogramming mode, where the flash memory is handled bythe central processing unit (CPU).As shown in Figure 4, the flash memory is divided into severalblocks, and erasure per block is possible.This internal flash memory has the boot ROM area storing the repro-gramming control software for reprogramming in the CPU repro-gramming mode and flash memory serial I/O mode, as well as theuser ROM area storing a certain control software for the normal op-eration in the microcomputer mode.Although our reprogramming control firmware for the flash memoryserial I/O mode has been stored into this boot ROM area on ship-ment, the user-original reprogramming control software which ismore appropriate for the user’s system is reprogrammable into thisarea, instead. Note that the reprogramming for the boot ROM area isenabled only in the flash memory parallel I/O mode.001000160010001628 Kbytes007FFF160080001600FFFF1600BFFF1600C0001600DFFF1600E0001600FFFF1616 Kbytes8 Kbytes8 KbytesFig. 4 M37906F8CFP, M37906F8CSP: block configuration of internal flash memory12

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

Flash Memory Parallel I/O Mode

The flash memory parallel I/O mode is used to manipulate the inter-nal flash memory with a parallel programmer. This parallel program-mer uses the software commands listed in Table 1 to do the flashmemory manipulations, such as read/programming/erase opera-tions.

User ROM Area and Boot ROM Area

The user ROM area and boot ROM area can be reprogrammed inthe flash memory parallel I/O mode.

The programming and block erase operations can be performed onlyto these areas.

The boot ROM area, 8 Kbytes in size, is assigned to addresses000016–1FFF16, so that programming and block erase operationscan be performed only to this area. (Access to any address out ofthis area is prohibited).

The erasable block in the boot ROM area is only one block, consist-ing of 8 Kbytes. The reprogramming control firmware to be used inthe flash memory serial I/O mode has been stored to this boot ROMarea on our shipment. Therefore, do not reprogram the boot ROMarea if the user uses the flash memory serial I/O mode.

Do not program to addresses FF9016 to FF9F16 because this area isthe reserved area for the programmer.

Note that, when the boot ROM area is read out from the CPU in theCPU reprogramming mode, described later, its addresses will beshifted to E00016—FFFF16.

Table 1. Software commands (flash memory parallel I/O mode) Software Command

Read Array

Read Status RegisterClear Status RegisterProgrammingBlock EraseErase All Block

Addresses FF9016 to FF9F16 are the reserved area for the parallelprogrammer. Therefore, when the user uses the flash memory paral-lel I/O mode, do not program to this area.

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Flash Memory Serial I/O Mode

In the flash memory serial I/O mode, addresses, data, and softwarecommands, which are required to read/program/erase the internalflash memory, are serially input and output with a fewer pins and thededicated serial programmer.

In this mode, being different from the flash memory parallel I/Omode, the CPU controls reprogramming of the flash memory (usingthe CPU reprogramming mode), serial input of the reprogrammingdata, etc.

The reprogramming control firmware for the flash memory serial I/Omode has been stored in the boot ROM area on shipment of theproduct from us. Note that, then, the flash memory serial I/O modewill become unavailable if the boot ROM area has been repro-grammed in the flash memory parallel I/O mode.

Note that, also, this reprogramming control firmware for the flashmemory serial I/O mode is subject to change.

Figures 5 and 6 show the pin connections in the flash memory serialI/O mode.

The three pins, SCLK, SDA, and BUSY, are used to input and outputserial data.

The SCLK pin is the input pin of external transfer clocks. The SDApin is the I/O pin of transmit and receive data, and its output acts asthe N-channel open-drain output. To the SDA pin, connect an exter-nal pullup resistor (about 1 kΩ). The BUSY pin is the output pin of theBUSY flag (CMOS output) and goes “H” during BUSY periods owingto a certain operation, such as transmit, receive, erase, program-ming, etc.

Transmit and receive data are serially transferred 8 bits at a time.In the flash memory serial I/O mode, only the user ROM area can bereprogrammed; the boot ROM area is not accessible.

Addresses FF9016 to FF9F16 are the reserved area for the serialprogrammer. Therefore, when the user uses the flash memory serialI/O mode, do not program to this area.

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VCCVREFAVss(Note 1)P74/AN4/DA1/INT3/RTPTRG0P73/AN3/DA0P72/AN2P71/AN1P70/AN0P65/TA2IN/U/RTP11P/TA2OUT/V/RTP10P63/TA1IN/W/RTP03P62/TA1OUT/U/RTP02P61/TA0IN/V/RTP01P60/TA0OUT/W/RTP00P57/INT7/TB2IN/IDU(Note 1)P56/INT6/TB1IN/IDVP55/INT5/TB0IN/IDW(Note 3)P6OUTCUT/INT4MD0VCONTRESETVcc1234567101112131415161718192021424140393837363534333231302928272625242322RESETAVccP10/CTS0/RTS0P11/CTS0/CLK0P12/RXD0P13/TXD0P14/CTS1/RTS1P15/CTS1/CLK1P16/RXD1P17/TXD1P20/TA4OUTP21/TA4INP22/TA9OUTP23/TA9INP24(/TB0IN)P25(/TB1IN)P26(/TB2IN)P27(/INT3/RTPTRG0)MD1XOUT(Note 2)XINVssOutline 42P2R-EFig. 5 Pin connection of M37906F8CFP in flash memory serial I/O mode (outline: 42P2R-E)

M37906F8CFPSCLKSDABUSYMD1(Note 1)VSSNotes 1: Allocation of pins TB0IN to TB2INand INT3/RTPTRG0 can be switched by software.2: Connected to the oscillation circuit.3: Recommended to be connected with VCC via a resistor.: Connected to a serial programmer.15

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VCCVREFAVss(Note 1)P74/AN4/DA1/INT3/RTPTRG0P73/AN3/DA0P72/AN2P71/AN1P70/AN0P65/TA2IN/U/RTP11P/TA2OUT/V/RTP10P63/TA1IN/W/RTP03P62/TA1OUT/U/RTP02P61/TA0IN/V/RTP01P60/TA0OUT/W/RTP00P57/INT7/TB2IN/IDU(Note 1)P56/INT6/TB1IN/IDVP55/INT5/TB0IN/IDW(Note 3)P6OUTCUT/INT4MD0VCONTRESETVcc1234567101112131415161718192021424140393837363534333231302928272625242322RESETAVccP10/CTS0/RTS0P11/CTS0/CLK0P12/RXD0P13/TXD0P14/CTS1/RTS1P15/CTS1/CLK1P16/RXD1P17/TXD1P20/TA4OUTP21/TA4INP22/TA9OUTP23/TA9INP24(/TB0IN)P25(/TB1IN)P26(/TB2IN)P27(/INT3/RTPTRG0)MD1XOUT(Note 2)XINVssNotes 1: Allocation of pins TB0IN to TB2INand INT3/RTPTRG0 can be switched by software.2: Connected to the oscillation circuit.3: Recommended to be connected with VCC via a resistor.: Connected to a serial programmer.Outline 42P4BFig. 6 Pin connection of M37906F8CSP in flash memory serial I/O mode (outline: 42P4B)M37906F8CSPSCLKSDABUSYMD1(Note 1)VSS16

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CPU Reprogramming Mode

The CPU reprogramming mode is used to perform the operations forthe internal flash memory (reading, programming, erasing) undercontrol of the CPU.

In this mode, only the user ROM area can be reprogrammed; theboot ROM area cannot be reprogrammed.

The user-original reprogramming control software for the CPU repro-gramming mode can be stored in either the user ROM area or theboot ROM area.

Because the CPU cannot read out the flash memory in the CPU re-programming mode, the above software must be transferred to theinternal RAM in advance to be executed.

Boot Mode

The user-original reprogramming control software for the CPU repro-gramming mode must be stored into the user ROM area or the bootROM area in the flash memory parallel I/O mode in advance. (If thisprogram has been stored into the boot ROM area, the flash memoryserial I/O mode will become unavailable).

Note that addresses of the boot ROM area depend on the accessingways to the boot ROM area, When accessing in the flash memoryparallel I/O mode, these addresses will be shifted to 000016 to1FFF16. On the other hand, when accessing with the CPU, these ad-dresses will be shifted to E00016 to FFFF16.

Reset removal with both of the MD0 and MD1 pins held “L” invokesthe normal microcomputer mode, and the CPU operates using thecontrol software stored in the user ROM area. In this case, the bootROM area is not accessible.

Removing reset with the MD0 pin held “L” and the MD1 pin “H”, theCPU starts its operation using the reprogramming control softwarestored in the boot ROM area. This mode is called the boot mode. Thereprogramming control software in the boot ROM area can also re-program the user ROM area.

After reset removal, be sure not to change the status at pins MD0and MD1.

76543210Flash memory control registerAddress9E16RY/BY status bit 0: Busy (Programming or erasing is active.) 1: ReadyCPU reprogramming mode select bit (Note 2) 0: Normal mode (Software commands are ignored.) 1: CPU reprogramming mode (Software commands are acceptable.)Flash memory reset bit (Note 3) 0: Normal operation 1: ResetUser ROM area select bit (Note 4)(Valid only in the boot mode.) 0: Boot ROM area access 1: User ROM area accessNotes 1: The contents of the flash memory control register after reset is removed are “XX000001”. 2: To set “1”, writing of “0” to bit 1 and subsequent writing of “1” to bit 1 are necessary. Writing to bit 1 must be performed by the user-original reprogramming control software in the internal RAM. 3: This bit is valid only when bit 1 = “1”. Before setting this bit to “0”, be sure to confirm that bit 0 = “1” after setting this bit to “1” (reset). This bit 3 must be controlled with bit 1 = “1”. 4: Writing to bit 5 must be performed by the user-original reprogramming control software in the internal RAM.Fig. 7 Bit configuration of flash memory control register

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Function overview (CPU reprogramming mode)The CPU reprogramming mode is available in the single-chip mode,memory expansion mode, and boot mode to reprogram the userROM area only.

In the CPU reprogramming mode, the CPU erases, programs, andreads the internal flash memory by writing software commands. Notethat the user-original reprogramming control software must be trans-ferred to the internal RAM in advance to be executed.

The CPU reprogramming mode becomes active when “1” is writteninto the flash memory control register’s bit 1 (the CPU reprogram-ming mode select bit) shown in Figure 7, and software commandsbecome acceptable.

In the CPU reprogramming mode, software commands and data areall written to and read from even addresses (Note that address A0 inbyte addresses = “0”.) 16 bits at a time. Therefore, a software com-mand consisting of 8 bits must be written to an even address; there-fore, any command written to an odd address will be invalid. Sincethe write data at the 2nd cycle of a programming command consistsof 16 bits, this data must be written to even and odd addresses.The seaquencer in the flash memory controls the erase and pro-gramming operations. What the status of the seaquencer operationis and whether the programming or erase operation has been com-pleted normally or terminated by an error can be examined by read-ing the flash memory control register.

Figure 7 shows the bit configuration of the flash memory control reg-ister.

Bit 0 (the RY/BY status bit) is a read-only bit for indicating the sea-quencer operation. This bit goes to “0” (BUSY) while the automaticprogramming/erase operation is active and goes to “1” (READY) dur-ing the other operations.

Bit 1 serves as the CPU reprogramming mode select bit. Writing of“1” to this bit selects the CPU reprogramming mode, and softwarecommands will be acceptable. Because the CPU cannot directly ac-cess the internal flash memory in the CPU reprogramming mode,writing to this bit 1 must be performed by the user-original repro-gramming control software which has been transferred to the inter-nal RAM in advance. To set bit 1 to “1”, it is necessary to write “0” and“1” to this bit 1 successively. On the other hand, to clear this bit to “0”,it is sufficient only to write “0”.

Bit 3 (the flash memory reset bit) resets the control circuit of the in-ternal flash memory and is used when the CPU reprogrammingmode is terminated or when an abnormal access to the flashmemory happens. Writing of “1” to bit 3 with the CPU reprogrammingmode select bit = “1” preforms the reset operation. To remove thereset, write “0” to bit 3 after confirming bit 0 (the RY/BY status bit) be-comes “1”.

Bit 5 serves as the user ROM area select bit and is valid only in theboot mode. Setting this bit to “1” in the boot mode switches an acces-sible area from the boot ROM area to the user ROM area. To use theCPU reprogramming mode in the boot mode, set this bit to “1”. Notethat when the microcomputer is booted up in the user ROM area,only the user ROM area is accessible and bit 5 is invalid; on the otherhand, when the microcomputer is in the boot mode, bit 5 is valid in-dependent of the CPU reprogramming mode. To rewrite bit 5, ex-ecute the user-original reprogramming control software transferredto the internal RAM in advance.

Figure 8 shows the CPU reprogramming mode set/termination flow-

chart, and be sure to follow this flowchart. As shown in Note 1 of Fig-ure 8, before selecting the CPU reprogramming mode, set “0” to theprocessor mode register 1’s bit 7 (the internal ROM bus cycle selectbit) and set flag I to “1” to avoid an interrupt request input.

When a watchdog timer interrupt request is generated in the CPUreprogramming mode, when an input to the RESET pin is “L”, orwhen the software reset is performed, the flash memory control cir-cuit and flash memory control register will be reset.

When the flash memory is reset during the erase or programmingoperation, this operation is cancelled and the target block’s data willbe invalid. Just before writing a software command related to theerase/programming operation, be sure to write to the watchdogtimer. In the CPU reprogramming mode, be sure not to use the STPand WIT instructions.

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Software Commands

StartSingle-chip mode,Memory expansion mode,or Boot modeTable 2 lists the software commands.

By writing a software command after the CPU reprogramming modeselect bit has been set to “1”, erasing, programming, etc. can bespecified. Note that, at software commands’ input, the high-orderbyte (D8–D15) is ignored. (Except for the write data at the 2nd cycleof a programming command.)

Software commands are explained as below.

The processor mode register 1 is set (Note 1).Flag I is set to “1”.Read Array Command (FF16)

By writing command code “FF16” at the 1st bus cycle, the microcom-puter enters the read array mode. If an address to be read is input inthe next or the following bus cycles, the contents at the specified ad-dress are output to the data bus (D0 to D15) in a unit of 16 bits.

The read array mode is maintained until writing of another softwarecommand.

The user-original reprogramming control software for the CPU reprogramming mode is transferred to the internal RAM.Jump to the above software in the internal RAM.(The operations shown below will be executed by the above software in this RAM.)Read Status Register Command (7016)

Writing command code “7016” at the 1st bus cycle outputs the con-tents of the status register to the data bus (D0-D7) by a read at the2nd bus cycle.

The status register is explained later.

(Only in the boot mode.)The user ROM area select bit is set to “1”.Clear Status Register Command (5016)

Writing of “1” to the CPU reprogramming mode select bit.(Writing of “0” → Writing of “1”)This command clears two status bits (SR.4, 5) each of which is setto “1” to indicate that the operation has been terminated by an error.To clear these bits, write command code “5016” at the 1st bus cycle.

Operations such as erasing, programming are executed by using software commands.Programming Command (4016)

This command facilitates programming of 1 word (2 bytes) at a time.To initiate programming, write command code “4016” at the 1st buscycle; when write data is written in a unit of 16 bits at the 2nd buscycle, the address is specified at the same time. Upon completion ofdata writing, automatic programming (data programming and verifi-cation) operation is started.

The completion of the automatic programming operation is con-firmed by a read of the flash memory control register. The RY/BY sta-tus bit of the flash memory control register goes “0” during theautomatic programming operation; and also, it goes “1” after the endof it.

Before execution of the next command, be sure to confirm that theRY/BY status bit is set to “1” (READY). During the automatic pro-gramming operation, writing of commands and access to the flashmemory must not be performed.

When programming continuously, the programming command canbe executed with the read status register mode kept if there is noprogramming error. Simultaneously with start of the automatic pro-gramming, the read status register mode is automatically active. Inthis case, the read status register mode is retained until the next readarray command (FF16) is written or until the reset is performed byusing the flash memory reset bit.

Reading out the status register after the automatic programming op-eration is completed reports the result of it. For details, refer to thesection on the status register.

Figure 9 shows an example of the programming flowchart.

Additional programming to any word that has already been pro-grammed is prohibited.

Read array command is executed, or reset is performed by setting the flash memory reset bit.(Writing of “1” → Writing of “0”) (Note 2)Writing of “0” to the CPU reprogramming mode select bit.(Only in the boot mode.)Writing of “0” to user ROM area select bit (Note 3).CompletedNotes 1: The processor mode register 1’s bit 7 (address 5F16, the internal ROM bus cycle select bit) must be “0” (bus cycle = 3φ).2: To terminate the CPU reprogramming mode after the erase and programming operations have been completed, be sure to execute the read array command or perform the flash memory reset operation.3: This bit may remain “1”. However, if this bit is “1”, the user ROM area access is specified.Fig. 8 CPU reprogramming mode set/termination flowchart

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Table 2. Software commands (CPU reprogramming mode)

1st cycle

Command

Read Array

Read Status RegisterClear Status RegisterProgrammingBlock EraseErase All Block

ModeWriteWriteWriteWriteWriteWrite

AddressX (Note 2)

XXXXX

Data(D0 to D7)FF16701650101620162016

Mode—Read—WriteWriteWrite

2nd cycleAddress—X—Data—SRD (Note 3)—

WA (Note 4)WD (Note 4)BA (Note 5)D016

X

2016

Notes 1: At software commands’ input, the high-order byte of data (D8–D15) is ignored.

2: X = An arbitrary address in the user ROM area. (Note that A0 = “0”.)3: SRD = Status Register Data

4: WA = Write Address, WD = Write Data (16 bits).

5: Block address: the maximum address of each block must be input. Note that address A0 = “0”.

Block Erase Command (2016/D016)

Writing command code “2016” at the 1st bus cycle and writing confir-mation command code “D016” and the maximum address of theblock (Note that address A0 = “0”.) at the subsequent 2nd bus cycleinitiate the automatic erase (erasing and erase verification) operationfor the specified block.

The completion of the automatic erase operation is confirmed by aread of the flash memory control register. The RY/BY status bit of theflash memory control register goes “0” simultaneously with start ofthe automatic erase operation; and also, it goes “1” simultaneouslywith completion of it.

Before execution of the next command, be sure to confirm that theRY/BY status bit is set to “1” (READY). During the automatic eraseoperation, writing of commands and access to the flash memorymust not be performed.

Simultaneously with start of the automatic erase, the read status reg-ister mode is automatically active. In this case, the read status regis-ter mode is retained until the next read array command (FF16) iswritten or until the reset is performed by using the flash memory re-set bit.

Reading out the status register after the automatic erase operationis completed reports the result of it. For details, refer to the sectionon the status register.

Figure 10 shows an example of the block erase flowchart.

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Erase All Block Command (2016/2016)

StartWrite 4016Write, Address, DataFlash memory controlregister ReadNOWriting command code “2016” at the 1st bus cycle and writing com-mand code “2016” at the subsequent 2nd bus cycle initiate the con-tinuous block erase (chip erase) operations for all the blocks.

The completion of the chip erase operation, as well as of the blockerase operation, is confirmed by a read of the flash memory controlregister. The result of the automatic erase operation is also reportedby a read of the status register.

During the automatic erase operation (when the RY/BY status bit =“0”), writing of commands and access to the flash memory must notbe performed.

RY/BY Status Bit = 1?YESStatus Register

The status register is used to indicate whether the programming/erase operation has been completed normally or terminated by anerror. By writing the read status register command (7016), the con-tents of the status register can be read out; by writing the clear sta-tus register command (5016), the contents of the status register canbe cleared.

Table 3 lists the definition of each bit of the status register.The status register outputs “8016” after reset is removed.The status of each bit is described below.

Full status checkProgramming CompletedFig. 9 Programming flowchartStartWrite 2016Write D016,Block addressFlash memory control register ReadNORY/BY Status Bit = 1?YESFull status checkBlock erase CompletedFig. 10 Block erase flowchart

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Erase Status Bit (SR.5)

This bit reports the status of the automatic erase operation. This bitis set to “1” if an erase error occurs and returns to “0” if the clear sta-tus register command (5016) is written.

(1) when data other than “D016” and “FF16” is written to the data in

the 2nd bus cycle of the block erase command (2016/D016)

(2) when data other than “2016” and “FF16” is written to the data in

the 2nd bus cycle of the erase all block command(2016/2016)Note that, writing of “FF16” forces the microcomputer into the readarray mode. Simultaneously with this, the command written in the 1stbus cycle will be canceled.

Programming Status Bit (SR.4)

This bit reports the status of the automatic programming operation.This bit is set to “1” if a programming error occurs and returns to “0”if the clear status register command (5016) is written.

Under the condition that any of SR.5, SR.4 = “1”, none of the pro-gramming, block erase, and erase all block commands can be ac-cepted. Before execution of these commands, execute the clearstatus register command (5016), in advance, to clear these statusbits.

Both of SR.4, SR.5 are set to “1” under the following conditions(Command Sequence Error):

Full Status Check

The full status check reports the results of the erase or programmingoperation.

Figure 11 shows the full status check flowchart and actions to betaken if an error has occurred.

Table 3. Bit definition of status register

SymbolSR.7 (D7)SR.6 (D6)SR.5 (D5)SR.4 (D4)SR.3 (D3)SR.2 (D2)SR.1 (D1)SR.0 (D0)

ReservedReserved

Erase Status

Programming StatusReservedReservedReservedReserved

Terminated by error.Terminated by error.

Terminated normally.Terminated normally.

Status

Definition

“1”

“0”

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Status Register ReadSR.4 = 1andSR.5 = 1?NOSR.5 = 0?YESSR.4 = 0?YESYESCommand SequenceError➀ Execute the clear status register command (5016) to clear the status register.➁ Confirm whether the command has correctly been input or not; and then, start the operation again.Perform the block erase operation again.If an error occurs even after the above operation is performed, the block cannot be used. NOBlock Erase ErrorNOProgramming ErrorPerform the programming operation again.If an error occurs even after the above operation is performed, the word cannot be used. End(Block erase, Programming)Note: Under the condition that any of SR.5 and SR.4 = “1”, none of the programming, block erase, and erase all block commands can be accepted. Before execution of these commands, execute the clear status register command (5016) in advance.Fig. 11 Full status check flowchart and actions to be taken if an error has ocurred

DC Electrical Characteristics (VCC = 5 V ± 0.5 V, Ta = 0 to 60 °C, f(fsys) = 20 MHz (Note))

SymbolIcc1

Icc2Icc3Icc4

Parameter

VCC power source current (at read)VCC power source current (at write)

VCC power source current (at programming)VCC power source current (at erasing)

Min.

LimitsTyp.30

Max.48485454

UnitmAmAmAmA

Limits of VIH, VIL, VOH, VOL, IIH, and IIL for each pin are the same as those in the microcomputer mode.Note: f(fsys) indicates the system clcok (fsys) frequency.

AC Electrical Characteristics (VCC = 5 V ± 0.5 V, Ta = 0 to 60 °C, f(fsys) = 20 MHz (Note))

Parameter

256-byte programming timeBlock erase timeErase all block time

n = Number of blocks to be erased

The limits of parameters other than the above are same as those in the microcomputer mode.Note: f(fsys) indicates the system clock (fsys) frequency.

Min.

LimitsTyp.40.60.6 ✕ n

Max.4088 ✕ n

Unitmsss

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ABSOLUTE MAXIMUM RATINGS

SymbolVCCAVCCVIVOPdToprTstg

Power source voltageAnalog power source voltageInput voltage

P10–P17, P20–P27, P55–P57, P60–P65, P70–P74,

P6OUTCUT, VCONT, VREF, XIN, RESET, BYTE, MD0, MD1Parameter

Ratings–0.3 to 6.5–0.3 to 6.5–0.3 to VCC+0.3–0.3 to VCC+0.3

300–20 to 85–40 to 150

UnitVVVVmW°C°C

Output voltageP10–P17, P20–P27, P55–P57, P60–P65, P70–P74, XOUTPower dissipation

Operating ambient temperatureStorage temerature

RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = –20 to 85 °C, unless otherwise noted)

SymbolVCCAVCCVSSAVSSVIHVILIOH(peak)IOH(avg)IOL(peak)IOL(peak)IOL(avg)IOL(avg)f(XIN)f(fsys)

Power source voltageAnalog power source voltagePower source voltage

Analog power source voltage

High-level input voltageP10–P17, P20–P27, P55–P57, P60–P65, P70–P74,

P6OUTCUT, XIN, RESET, MD0, MD1Low-level input voltageP10–P17, P20–P27, P55–P57, P60–P65, P70–P74,

P6OUTCUT, XIN, RESET, MD0, MD1High-level peak output currentLow-level peak output currentLow-level peak output current

P10–P17, P20–P27, P55–P57, P60–P65, P70–P74P10–P17, P20–P27, P55–P57, P70–P74P60–P65

High-level average output currentP10–P17, P20–P27, P55–P57, P60–P65, P70–P74

0.8 Vcc0

Parameter

Limits

Min.4.5

Typ.5.0VCC00

Vcc0.2 VCC–10–510205152020Max.5.5

UnitVVVVVVmAmAmAmAmAmAMHzMHz

Low-level average output currentP10–P17, P20–P27, P55–P57, P70–P74Low-level average output currentP60–P65External clock input frequency (Note 1)System clock frequency

Notes 1: When using the PLL frequency multiplier, be sure that f(fsys) = 20 MHz or less.

2: The average output current is the average value of an interval of 100 ms.

3: The sum of IOL(peak) must be 110 mA or less, the sum of IOH(peak) must be 80 mA or less.

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

DC ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz)

SymbolVOH

Parameter

High-level output voltageP10–P17, P20–P27,P55–P57, P60–P65,P70–P74Low-level output voltageP10–P17, P20–P27,P55–P57, P60–P65,P70–P74Hysteresis

TA0IN–TA2IN, TA4IN, TA9IN,

TA0OUT–TA2OUT, TA4OUT, TA9OUT,TB0IN–TB2IN, INT3–INT7, CTS0,CTS1, CLK0, CLK1, RxD0, RxD1,RTPTRG0, P6OUTCUT

Test conditions

IOH = –10 mA

Min.3

LimitsTyp.

Max.

UnitV

VOLIOL = 10 mA2V

VT+ —VT–

0.41V

VT+ —VT–VT+ —VT–IIH

HysteresisRESETHysteresisXIN

High-level input currentP10–P17, P20–P27,

P55–P57, P60–P65,

P70–P74, P6OUTCUT, XIN,RESET, MD0, MD1Low-level input currentP10–P17, P20–P27,

P55–P57, P60–P65,

P70–P74, P6OUTCUT, XIN,RESET, MD0, MD1RAM hold voltagePower source current

VI = 5.0 V

0.50.1

1.50.35

VV

µA

IILVI = 0 V–5µA

VRAMICC

When clock is inactive.Output-only pinsare open, and theother pins are con-nected to Vss orVcc. An externalsquare-waveformclock is input. (PinXOUT is open.) ThePLL frequencymultiplier is inac-tive.f(fsys) = 20 MHz.CPU is active.Ta = 25 °C whenclock is inactive.Ta = 85 °C whenclock is inactive.

2

25

50

VmA

1µA

20

25

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

A-D CONVERTER CHARACTERISTICS(VCC = AVCC = 5 V ± 0.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)Symbol—————ParameterResolutionVREF = VCCTest conditionsA-D converterComparator10-bit resolution mode8-bit resolution modeComparater510-bit resolution mode8-bit resolution modeComparater5.92.45 (Note)0.7 (Note)2.70VCCVREFVVLimitsMin.Typ.Max.10UnitBits—————RLADDERtCONVVREFVIAAbsolute accuracyLadder resistanceConversion timeReference voltageAnalog input voltageVREF = VCCVREF = VCCf(fsys) ≤ 20 MHz1VREFV256± 3LSB± 2LSB± 40mVkΩµsNote: This is applied when A-D conversion freguency (φAD) = f1 (φ).D-A CONVERTER CHARACTERISTICS(VCC = 5 V, VSS = AVSS = 0 V, VREF = 5 V, Ta = –20 to 85 °C, unless otherwise noted)Symbol————tsuROIVREFResolutionAbsolute accuracySet timeOutput resistanceReference power source input current(Note)23.5ParameterTest conditionsMin.LimitsTyp.Max.8± 1.034.53.2UnitBits%µskΩmANote: The test conditions are as follows:• One D-A converter is used.• The D-A register value of the unused D-A converter is “0016.”• The reference power source input current for the ladder resistance of the A-D converter is excluded.RESET INPUTReset input timing requirements (VCC = 5 V ± 0.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)Symboltw(RESETL)ParameterRESET input low-level pulse widthMin.10LimitsTyp.Max.UnitµsRESET inputtw(RESETL)26

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

PERIPHERAL DEVICE INPUT/OUTPUT TIMING

(VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz unless otherwise noted)

For limits depending on f(fsys), their calculation formulas are shown below. Also, the values at f(fsys) = 20 MHz are shown in ( ).

Timer A input (Count input in event counter mode)

Symboltc(TA)tw(TAH)tw(TAL)

TAiIN input cycle time

TAiIN input high-level pulse widthTAiIN input low-level pulse width

Parameter

LimitsMin.804040

Max.

Unitnsnsns

Timer A input (Gating input in timer mode)

Symboltc(TA)tw(TAH)tw(TAL)

TAiIN input cycle time

TAiIN input high-level pulse widthTAiIN input low-level pulse width

Parameter

f(fsys) ≤ 20 MHzf(fsys) ≤ 20 MHzf(fsys) ≤ 20 MHz

Limits

Min.16 × 109f(fsys)8 × 109f(fsys)8 × 109f(fsys)(800)(400)(400)

Max.

Unitnsnsns

Note :The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width

respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz.

Timer A input (External trigger input in one-shot pulse mode)

Symboltc(TA)tw(TAH)tw(TAL)

TAiIN input cycle time

TAiIN input high-level pulse widthTAiIN input low-level pulse width

Parameter

f(fsys) ≤ 20 MHz

Limits

Min.8 × 109f(fsys)8080

(400)

Max.

Unitnsnsns

Timer A input (External trigger input in pulse width modulation mode)

Symboltw(TAH)tw(TAL)

TAiIN input high-level pulse widthTAiIN input low-level pulse width

Parameter

LimitsMin.8080

Max.

Unitnsns

Timer A input (Up-down input and Count input in event counter mode)

Symboltc(UP)tw(UPH)tw(UPL)tsu(UP-TIN)th(TIN-UP)

TAiOUT input cycle time

TAiOUT input high-level pulse widthTAiOUT input low-level pulse widthTAiOUT input setup timeTAiOUT input hold time

Parameter

LimitsMin.200010001000400400

Max.

Unitnsnsnsnsns

27

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

Timer A input (Two-phase pulse input in event counter mode)Symboltc(TA)tsu(TAjIN-TAjOUT)tsu(TAjOUT-TAjIN)TAjIN input cycle timeTAjIN input setup timeTAjOUT input setup timeParameterLimitsMin.800200200Max.Unitnsnsns• Gating input in timer mode• Count input in event counter mode• External trigger input in one-shot pulse mode• External trigger input in pulse width modulation modetc(TA)tw(TAH)TAiIN inputtw(TAL)• Up-down and Count input in event counter modetc(UP)tw(UPH)TAiOUT input(Up-down input)tw(UPL)TAiOUT input(Up-down input)TAiIN input(When count by falling)th(TIN-UP)tsu(UP-TIN)TAiIN input(When count by rising)• Two-phase pulse input in event counter modetc(TA)TAjIN inputtsu(TAjIN-TAjOUT)TAjOUT inputtsu(TAjIN-TAjOUT)tsu(TAjOUT-TAjIN)tsu(TAjOUT-TAjIN)Test conditions • VCC = 5 V ± 0.5 V, Ta = –20 to 85 °C • Input timing voltage : VIL = 1.0 V, VIH = 4.0 V28

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

Timer B input (Count input in event counter mode)

Symboltc(TB)tw(TBH)tw(TBL)tc(TB)tw(TBH)tw(TBL)

TBiIN input cycle time (one edge count)

TBiIN input high-level pulse width (one edge count)TBiIN input low-level pulse width (one edge count)TBiIN input cycle time (both edge count)

TBiIN input high-level pulse width (both edge count)TBiIN input low-level pulse width (both edge count)

Parameter

LimitsMin.8040401608080

Max.

Unitnsnsnsnsnsns

Timer B input (Pulse period measurement mode)

Symboltc(TB)tw(TBH)tw(TBL)

TBiIN input cycle time

TBiIN input high-level pulse widthTBiIN input low-level pulse width

Parameter

f(fsys) ≤ 20 MHzf(fsys) ≤ 20 MHzf(fsys) ≤ 20 MHz

Limits

Min.16 × 109

(800)

f(fsys)8 × 109f(fsys)8 × 109f(fsys)(400)(400)

Max.

Unitnsnsns

Note:The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width

respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz.

Timer B input (Pulse width measurement mode)

Symboltc(TB)tw(TBH)tw(TBL)

TBiIN input cycle time

TBiIN input high-level pulse widthTBiIN input low-level pulse width

Parameter

f(fsys) ≤ 20 MHzf(fsys) ≤ 20 MHzf(fsys) ≤ 20 MHz

Limits

Min.16 × 109

(800)

f(fsys)8 × 109f(fsys)8 × 109f(fsys)(400)(400)

Max.

Unitnsnsns

Note:The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width

respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz.

Serial I/O

Symboltc(CK)tw(CKH)tw(CKL)td(C-Q)th(C-Q)tsu(D-C)th(C-D)

CLKi input cycle time

CLKi input high-level pulse widthCLKi input low-level pulse widthTXDi output delay timeTXDi hold timeRXDi input setup timeRXDi input hold time

02090

Parameter

LimitsMin.200100100

80Max.

Unitnsnsnsnsnsnsns

29

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

External interrupt (INTi) inputSymboltw(INH)tw(INL)INTi input high-level pulse widthINTi input low-level pulse widthParameterLimitsMin.250250Max.Unitnsnstc(TB)tw(TBH)TBiIN inputtw(TBL)tc(CK)tw(CKH)CLKi inputtw(CKL)th(C-Q)TxDi outputtd(C-Q)RxDi inputtsu(D-C)th(C-D)tw(INL)INTi inputtw(INH)Test conditions • Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C • Input timing voltage : VIL = 1.0 V, VIH = 4.0 V • Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF30

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

External clock input

Timing Requirements (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Symboltctw(half)tw(H)tw(L)trtf

External clock input cycle time

External clock input pulse width with half input-volageExternal clock input high-level pulse widthExternal clock input low-level pulse widthExternal clock input rise timeExternal clock input fall time

Parameter

Limits

Min.500.45 tc0.5 tc – 80.5 tc – 8

880.55 tcMax.

Unitnsnsnsnsnsns

External clock inputtw(L)XINtw(H)trtftctw(half)Test conditions • Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C • Input timing voltage: VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf) • Input timing voltage: 2.5 V (tc, tw(half))31

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

PACKAGE OUTLINE42P2R-EEIAJ Package CodeSSOP42-P-450-0.8042Plastic 42pin 450mil SSOPJEDEC Code–Weight(g)0.6322Lead MaterialAlloy 42/Cu Alloyeb2HEEe1FRecommended Mount PadDimension in MillimetersMinNomMax2.4––––0.05–2.0–0.50.40.350.20.150.1317.717.517.38.68.48.2–0.8–12.2311.9311.630.70.50.3–1.765––0.75–––0.90.15––0°–10°–0.5––11.43––1.27–Symbol121AGDA2eybA1czZ1Detail GDetail FAA1A2bcDEeHELL1zZ1yb2e1I2L142P4BEIAJ Package CodeSDIP42-P-600-1.78JEDEC Code–Weight(g)4.1Lead MaterialAlloy 42/Cu AlloyLPlastic 42pin 600mil SDIP4222121SymbolDeSEATING PLANEb1bb2AA1A2bb1b2cDEee1LDimension in MillimetersMinNomMax––5.50.51–––3.8–0.350.450.550.91.01.30.630.731.030.220.270.3436.536.736.912.8513.013.15–1.778––15.24–3.0––0°–15°A32

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M37906F8CFP, M37906F8CSP

16-BIT CMOS MICROCOMPUTER

Keep safety first in your circuit designs!•Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble withsemiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement ofsubstitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.Notes regarding these materials•••These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under anyintellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuitapplication examples contained in these materials.All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject tochange by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorizedMitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from theseinaccuracies or errors.Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before makinga final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contactMitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems fortransportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than theapproved destination.Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.•••••© 2001 MITSUBISHI ELECTRIC CORP.New publication, effective Jun., 2001.

Specifications subject to change without notice.

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REVISION HISTORY

Rev.1.02.0

Date

Page

3/02/016/26/01

——1

M37906F8CFP/SP DATASHEET

Description

Summary

First Edition

Some English expressions and the following are corrected:•DESCRIPTION; line 3

•••• silicon gate technology, being packaged ••••

•••• silicon gate technology, including the internal flash memory andbeing packaged ••••

17

•Figure 7; Note 3

•••• after setting this bit to “1” (reset).

•••• after setting this bit to “1” (reset). This bit 3 must be controlled

with bit 1 = “1”.

19

•Programming Command (4016); lines 18,19

•••• be executed with the read status register mode kept. ••••

•••• be executed with the read status register mode kept if there isno programming error. ••••

23

•Figure 11

Status Register Error Status Register Read(1/1)

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