SN54HC2资料

SN54HC259, SN74HC2598ĆBIT ADDRESSABLE LATCHESSCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003DWide Operating Voltage Range of 2 V to 6 VDHigh-Current Inverting Outputs Drive Up ToDDDDDDDDDD10 LSTTL LoadsLow Power Consumption, 80-µA Max ICCTypical tpd = 14 ns±4-mA Output Drive at 5 VLow Input Current of 1 µA Max8-Bit Parallel-Out Storage RegisterPerforms Serial-to-Parallel Conversion WithStorageAsynchronous Parallel ClearActive-High DecoderEnable Input Simplifies ExpansionExpandable for n-Bit ApplicationsFour Distinct Functional ModesSN54HC259...J OR W PACKAGESN74HC259...D, N, NS, OR PW PACKAGE(TOP VIEW)S0S1S2Q0Q1Q2Q3GND12345678161514131211109VCCCLRGDQ7Q6Q5Q4SN54HC259...FK PACKAGE(TOP VIEW)description/ordering informationThese 8-bit addressable latches are designed forgeneral-purpose storage applications in digitalsystems. Specific uses include working registers,serial-holding registers, and active-high decodersor demultiplexers. They are multifunctionaldevices capable of storing single-line data in eightaddressable latches and being a 1-of-8 decoderor demultiplexer with active-high outputs.ORDERING INFORMATIONTAPDIP − NSOIC − D−40°C to 85°CSOP − NSTSSOP − PWCDIP − J−55°C to 125°CCFP − WLCCC − FKPACKAGE†Tube of 25Tube of 40Reel of 2500Reel of 250Reel of 2000Reel of 2000Reel of 250Tube of 25Tube of 150Tube of 55S2Q0NCQ1Q2S1S0NCVCCCLR4567832120191817161514910111213GDNCQ7Q6NC − No internal connectionORDERABLEPART NUMBERSN74HC259NSN74HC259DSN74HC259DRSN74HC259DTSN74HC259NSRSN74HC259PWRSN74HC259PWTSNJ54HC259JSNJ54HC259WSNJ54HC259FK†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines areavailable at www.ti.com/sc/package.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright  2003, Texas Instruments IncorporatedOn products compliant to MILĆPRFĆ38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•Q3GNDNCQ4Q5TOP-SIDEMARKINGSN74HC259NHC259HC259HC259SNJ54HC259JSNJ54HC259WSNJ54HC259FK1元器件交易网www.cecb2b.com

SN54HC259, SN74HC2598ĆBIT ADDRESSABLE LATCHESSCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003description/ordering information (continued)Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs. In theaddressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latchfollows the data input, with all unaddressed latches remaining in their previous states. In the memory mode, alllatches remain in their previous states and are unaffected by the data or address inputs. To eliminate thepossibility of entering erroneous data in the latches, G should be held high (inactive) while the address linesare changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of theD input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and datainputs.Function TablesFUNCTIONINPUTSCLRHHLLGLHLHOUTPUT OFADDRESSEDLATCHDQiODLEACHOTHEROUTPUTQiOQiOLLFUNCTIONAddressable latchMemory8-line demultiplexerClearLATCH SELECTIONSELECT INPUTSS2LLLLHHHHS1LLHHLLHHS0LHLHLHLHLATCHADDRESSED012345672POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com

SN54HC259, SN74HC2598ĆBIT ADDRESSABLE LATCHESSCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003logic diagramS01DCRDCRDCRDCRS23DCRDCRG14DCRD13DCRCLR15Q12Q7Q11Q6Q9Q4Q4Q0Q5Q1S12Q6Q2Q7Q3Q10Q5Pin numbers shown are for the D, J, N, NS, PW, and W packages.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.com

SN54HC259, SN74HC2598ĆBIT ADDRESSABLE LATCHESSCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003logic diagram, each internal latch (positive logic)CDCCTGCQCCTGRCabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 VInput clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAOutput clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAContinuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mAContinuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAPackage thermal impedance, θJA (see Note 2):D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/WN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/WNS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C/WPW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/WStorage temperature range, Tstg −65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.2.The package thermal impedance is calculated in accordance with JESD 51-7.recommended operating conditions (see Note 3)SN54HC259MINVCCVIHSupply voltageHigh-level input voltageVCC = 2 VVCC = 4.5 VVCC = 6 VVCC = 2 VVILVIVO∆t/∆vLow-level input voltageInput voltageOutput voltageInput transition rise/fall timeVCC = 2 VVCC = 4.5 VVCC = 6 VVCC = 4.5 VVCC = 6 V0021.53.154.20.51.351.8VCCVCC100050040000NOM5MAX6SN74HC259MIN21.53.154.20.51.351.8VCCVCC1000500400nsVVVVNOM5MAX6UNITVTAOperating free-air temperature−55125−4085°CNOTE 3:All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com

SN54HC259, SN74HC2598ĆBIT ADDRESSABLE LATCHESSCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERTEST CONDITIONSVCC2 VIOH = −20 µAVOHVI = VIH or VILIOH = −4 mAIOH = −5.2 mAIOL = 20 µAVOLVI = VIH or VILIOL = 4 mAIOL = 5.2 mAIIICCCiVI = VCC or 0VI = VCC or 0,IO = 04.5 V6 V4.5 V6 V2 V4.5 V6 V4.5 V6 V6 V6 V2 V to 6 V3TA = 25°CMINTYPMAX1.94.45.93.985.481.9984.4995.9994.35.80.0020.0010.0010.170.15±0.10.10.10.10.260.26±100810SN54HC259MIN1.94.45.93.75.20.10.10.10.40.4±100016010MAXSN74HC259MIN1.94.45.93.845.340.10.10.10.330.33±10008010nAµApFVVMAXUNITtiming requirements over recommended operating free-air temperature range (unless otherwisenoted)VCC2 VCLR lowtwPulse durationG low4.5 V6 V2 V4.5 V6 V2 VtsuSetup time, data or address before G↑4.5 V6 V2 VthHold time, data or address after G↑4.5 V6 VTA = 25°CMINMAX801614801614751513555SN54HC259MIN120242012024201152320555MAXSN74HC259MIN10020171002017951916555nsnsnsMAXUNITPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5元器件交易网www.cecb2b.com

SN54HC259, SN74HC2598ĆBIT ADDRESSABLE LATCHESSCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003switching characteristics over recommended operating free-air temperature range, CL = 50 pF(unless otherwise noted) (see Figure 1)PARAMETERFROM(INPUT)TO(OUTPUT)VCC2 VtPHLCLRAny Q4.5 V6 V2 VDataAny Q4.5 V6 V2 VtpdAddressAny Q4.5 V6 V2 VGAny Q4.5 V6 V2 VttAny4.5 V6 VTA = 25°CMINTYPMAX60181456171374211766201628861503026130262220040341703429751513SN54HC259MINMAX22545381953933300605125551431102219SN74HC259MINMAX1903832165332825050432154337951916nsnsnsUNIToperating characteristics, TA = 25°CPARAMETERCpdPower dissipation capacitance per latchTEST CONDITIONSNo loadTYP33UNITpF6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com

SN54HC259, SN74HC2598ĆBIT ADDRESSABLE LATCHESSCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003PARAMETER MEASUREMENT INFORMATIONHigh-LevelPulse50%twLow-LevelPulseVCC50%50%0 VVOLTAGE WAVEFORMSPULSE DURATIONSVCC50%tPLHReferenceInputtsuDataInput50%10%90%tr50%th90%VCC50%10%0 VtfOut-of-PhaseOutputVCC0 VIn-PhaseOutput50%10%tPHL90%50%10%tf90%trtPLH50%10%90%tr50%0 VtPHL90%50%10%VOLtfVOHVCC50%0 VFrom OutputUnder TestTestPointCL = 50 pF(see Note A)LOAD CIRCUITInputVOHVOLVOLTAGE WAVEFORMSSETUP AND HOLD AND INPUT RISE AND FALL TIMESVOLTAGE WAVEFORMSPROPAGATION DELAY AND OUTPUT TRANSITION TIMESNOTES:A.CL includes probe and test-fixture capacitance.B.Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the followingcharacteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.C.The outputs are measured one at a time with one input transition per measurement.D.tPLH and tPHL are the same as tpd.Figure 1. Load Circuit and Voltage WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•7元器件交易网www.cecb2b.com

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MECHANICAL DATAMCFP004A– JANUARY 1995 – REVISED FEBRUARY 2002W (R-GDFP-F16)CERAMIC DUAL FLATPACKBase and Seating Plane0.045 (1,14)0.026 (0,66)0.285 (7,24)0.245 (6,22)0.006 (0,15)0.080 (2,03)0.055 (1,40)0.305 (7,75) MAX1160.019 (0,48)0.015 (0,38)0.004 (0,10)0.050 (1,27)0.430 (10,92)0.370 (9,40)0.005 (0,13) MIN4 Places80.360 (9,14)0.250 (6,35)90.360 (9,14)0.250 (6,35)4040180-3/C 02/02NOTES:A.B.C.D.E.All linear dimensions are in inches (millimeters).This drawing is subject to change without notice.This package can be hermetically sealed with a ceramic lid using glass frit.Index point is provided on cap for terminal identification only.Falls within MIL STD 1835 GDFP-1F16 and JEDEC MO-092ACPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.com

MECHANICAL DATA MLCC006B – OCTOBER 1996FK (S-CQCC-N**) 28 TERMINAL SHOWNLEADLESS CERAMIC CHIP CARRIER18171615141312NO. OFTERMINALS**1110287668584445220AMIN0.342(8,69)0.442(11,23)0.0(16,26)0.739(18,78)0.938(23,83)1.141(28,99)MAX0.358(9,09)0.458(11,63)0.660(16,76)0.761(19,32)0.962(24,43)1.165(29,59)MIN0.307(7,80)0.406(10,31)0.495(12,58)0.495(12,58)0.850(21,6)1.047(26,6)BMAX0.358(9,09)0.458(11,63)0.560(14,22)0.560(14,22)0.858(21,8)1.063(27,0)192021B SQ22A SQ23242526272812340.080 (2,03)0.0 (1,63)0.020 (0,51)0.010 (0,25)0.020 (0,51)0.010 (0,25)0.055 (1,40)0.045 (1,14)0.045 (1,14)0.035 (0,)0.028 (0,71)0.022 (0,54)0.050 (1,27)0.045 (1,14)0.035 (0,)4040140/D 10/96NOTES:A.B.C.D.E.All linear dimensions are in inches (millimeters).This drawing is subject to change without notice.This package can be hermetically sealed with a metal lid.The terminals are gold plated.Falls within JEDEC MS-004POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.com

MECHANICALMPDI002C – JANUARY 1995 – REVISED DECEMBER 20002N (R-PDIP-T**) 16 PINS SHOWNPLASTIC DUAL-IN-LINE PACKAGEPINS **DIMA169A MAX140.775(19,69)0.745(18,92)160.775(19,69)0.745(18,92)180.920(23,37)0.850(21,59)201.060(26,92)0.940(23,88)A MIN0.260 (6,60)0.240 (6,10)CMS-100VARIATIONAABBACAD10.070 (1,78)0.045 (1,14)D80.045 (1,14)0.030 (0,76)D0.020 (0,51) MIN0.325 (8,26)0.300 (7,62)0.015 (0,38)0.200 (5,08) MAXSeating Plane0.125 (3,18) MIN0.010 (0,25) NOMGauge Plane0.100 (2,54)0.021 (0,53)0.015 (0,38)0.010 (0,25)M0.430 (10,92) MAX14/18 PIN ONLY20 pin vendor optionD4040049/E 12/2002NOTES:A.All linear dimensions are in inches (millimeters).B.This drawing is subject to change without notice.C.Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).D.The 20 pin end lead shoulder width is a vendor option, either half or full width.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.com

MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001 MECHANICAL DATA D (R-PDSO-G**) 8 PINS SHOWN0.050 (1,27)850.020 (0,51)0.014 (0,35)0.010 (0,25)PLASTIC SMALL-OUTLINE PACKAGE0.244 (6,20)0.228 (5,80)0.157 (4,00)0.150 (3,81)0.008 (0,20) NOMGage Plane1A40°– 8°0.044 (1,12)0.016 (0,40)0.010 (0,25)Seating Plane0.069 (1,75) MAX0.010 (0,25)0.004 (0,10)0.004 (0,10)PINS **DIMA MAXA MIN80.197(5,00)0.1(4,80)140.344(8,75)0.337(8,55)160.394(10,00)0.386(9,80)4040047/E 09/01NOTES:A.B.C.D.All linear dimensions are in inches (millimeters).This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).Falls within JEDEC MS-012POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.com

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MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 MECHANICAL DATA PW (R-PDSO-G**) 14 PINS SHOWNPLASTIC SMALL-OUTLINE PACKAGE0,651480,300,190,10M0,15 NOM4,504,306,606,20Gage Plane0,251A70°–8°0,750,50Seating Plane1,20 MAX0,150,050,10PINS **DIMA MAX83,10145,10165,10206,60247,902,80A MIN2,904,904,906,407,709,6040400/F 01/97NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion not to exceed 0,15.Falls within JEDEC MO-153POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.com

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