attiny4 attiny5 attiny9 attiny10

•High Performance, Low Power AVR® 8-Bit Microcontroller•Advanced RISC Architecture

–54 Powerful Instructions – Most Single Clock Cycle Execution

–16 x 8 General Purpose Working Registers–Fully Static Operation

–Up to 12 MIPS Throughput at 12 MHzNon-volatile Program and Data Memories

–512/1024 Bytes of In-System Programmable Flash Program Memory–32 Bytes Internal SRAM

•

8-bit –Flash Write/Erase Cycles: 10,000

–Data Retention: 20 Years at 85oC / 100 Years at 25oC•

Peripheral Features

–QTouch® Library Support for Capacitive Touch Sensing (1 Channel)–One 16-bit Timer/Counter with Prescaler and Two PWM Channels–Programmable Watchdog Timer with Separate On-chip Oscillator–4-channel, 8-bit Analog to Digital Converter (ATtiny5/10, only)–On-chip Analog Comparator•

Special Microcontroller Features

–In-System Programmable (at 5V, only)–External and Internal Interrupt Sources

–Low Power Idle, ADC Noise Reduction, and Power-down Modes–Enhanced Power-on Reset Circuit

–Programmable Supply Voltage Level Monitor with Interrupt and Reset–Internal Calibrated Oscillator•

I/O and Packages

–Four Programmable I/O Lines–6-pin SOT and 8-pad UDFN•Operating Voltage:–1.8 – 5.5V

•Programming Voltage:–5V

•

Speed Grade

–0 – 4 MHz @ 1.8 – 5.5V–0 – 8 MHz @ 2.7 – 5.5V–0 – 12 MHz @ 4.5 – 5.5V

•Industrial and Extended Temperature Ranges•

Low Power Consumption–Active Mode:

•200µA at 1MHz and 1.8V–IdleMode:

•25µA at 1MHz and 1.8V–Power-down Mode:

•< 0.1µA at 1.8V

Microcontroller with 512/1024 Bytes In-SystemProgrammable FlashATtiny4/5/9/10SummaryRev. 8127ES–AVR–11/111.Pin Configurations

Figure 1-1.

Pinout of ATtiny4/5/9/10

SOT-23(PCINT0/TPIDATA/OC0A/ADC0/AIN0) PB0 GND(PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1123654PB3 (RESET/PCINT3/ADC3)VCCPB2 (T0/CLKO/PCINT2/INT0/ADC2)UDFN(PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 NCNCGND12348765PB2 (T0/CLKO/PCINT2/INT0/ADC2)VCCPB3 (RESET/PCINT3/ADC3)PB0 (AIN0/ADC0/OC0A/TPIDATA/PCINT0)1.1

1.1.1

Pin Description

VCC

Supply voltage.

1.1.2GND

Ground.

1.1.3

Port B (PB3..PB0)

This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable foreach bit. The output buffers have symmetrical drive characteristics, with both high sink andsource capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even ifthe clock is not running.

The port also serves the functions of various special features of the ATtiny4/5/9/10, as listed onpage 37.

1.1.4RESETReset input. A low level on this pin for longer than the minimum pulse length will generate areset, even if the clock is not running and provided the reset pin has not been disabled. The min-imum pulse length is given in Table 16-4 on page 120. Shorter pulses are not guaranteed togenerate a reset.

The reset pin can also be used as a (weak) I/O pin.

2

ATtiny4/5/9/10

8127ES–AVR–11/11

ATtiny4/5/9/10

2.Overview

ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVRenhanced RISC architecture. By executing powerful instructions in a single clock cycle, theATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designerto optimize power consumption versus processing speed.Figure 2-1.

Block Diagram

VCCRESETPROGRAMMINGLOGICPROGRAMCOUNTERINTERNALOSCILLATORCALIBRATEDOSCILLATORPROGRAMFLASHSTACKPOINTERWATCHDOGTIMERTIMING ANDCONTROLINSTRUCTIONREGISTERSRAMRESET FLAGREGISTERINSTRUCTIONDECODERGENERALPURPOSEREGISTERSXYZMCU STATUSREGISTERCONTROLLINESTIMER/COUNTER0ALUINTERRUPTUNITISPINTERFACESTATUSREGISTER8-BIT DATA BUSDATA REGISTERPORT BDIRECTIONREG. PORT BANALOGCOMPARATORADCDRIVERSPORT BPB3:0GNDThe AVR core combines a rich instruction set with 16 general purpose working registers andsystem registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowingtwo independent registers to be accessed in one single instruction executed in one clock cycle.The resulting architecture is compact and code efficient while achieving throughputs up to tentimes faster than conventional CISC microcontrollers.

3

8127ES–AVR–11/11

The ATtiny4/5/9/10 provide the following features: 512/1024 byte of In-System ProgrammableFlash, 32 bytes of SRAM, four general purpose I/O lines, 16 general purpose working registers,a 16-bit timer/counter with two PWM channels, internal and external interrupts, a programmablewatchdog timer with internal oscillator, an internal calibrated oscillator, and four software select-able power saving modes. ATtiny5/10 are also equipped with a four-channel, 8-bit Analog toDigital Converter (ADC).

Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), ana-log comparator, and interrupt system to continue functioning. ADC Noise Reduction modeminimizes switching noise during ADC conversions by stopping the CPU and all I/O modulesexcept the ADC. In Power-down mode registers keep their contents and all chip functions aredisabled until the next interrupt or hardware reset. In Standby mode, the oscillator is runningwhile the rest of the device is sleeping, allowing very fast start-up combined with low powerconsumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip, in-system programmable Flash allows program memory to be re-programmed in-system bya conventional, non-volatile memory programmer.

The ATtiny4/5/9/10 AVR are supported by a suite of program and system development tools,including macro assemblers and evaluation kits.

2.1Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10

A comparison of the devices is shown in Table 2-1.Table 2-1.

Differences between ATtiny4, ATtiny5, ATtiny9 and ATtiny10

Flash512 bytes512 bytes1024 bytes1024 bytes

ADCNoYesNoYes

Signature0x1E 0x8F 0x0A0x1E 0x8F 0x090x1E 0x90 0x080x1E 0x90 0x03

DeviceATtiny4ATtiny5ATtiny9ATtiny10

4

ATtiny4/5/9/10

8127ES–AVR–11/11

ATtiny4/5/9/10

3.General Information

3.1

Resources

A comprehensive set of drivers, application notes, data sheets and descriptions on developmenttools are available for download at http://www.atmel.com/avr.

3.2Code Examples

This documentation contains simple code examples that briefly show how to use various parts ofthe device. These code examples assume that the part specific header file is included beforecompilation. Be aware that not all C compiler vendors include bit definitions in the header filesand interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-tation for more details.

3.3Capacitive Touch Sensing

Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on AtmelAVR microcontrollers. The QTouch Library includes support for QTouch® and QMatrix® acquisi-tion methods.

Touch sensing is easily added to any application by linking the QTouch Library and using theApplication Programming Interface (API) of the library to define the touch channels and sensors.The application then calls the API to retrieve channel information and determine the state of thetouch sensor.

The QTouch Library is free and can be downloaded from the Atmel website. For more informa-tion and details of implementation, refer to the QTouch Library User Guide – also available fromthe Atmel website.

3.4Data Retention

Reliability Qualification results show that the projected data retention failure rate is much lessthan 1 PPM over 20 years at 85°C or 100 years at 25°C.

5

8127ES–AVR–11/11

4.Register Summary

Address

0x3F0x3E0x3D0x3C0x3B0x3A0x390x380x370x360x350x340x330x320x310x300x2F0x2E0x2D0x2C0x2B0x2A0x290x280x270x260x250x240x230x220x210x200x1F0x1E0x1D0x1C0x1B0x1A0x190x180x170x160x150x140x130x120x110x100x0F0x0E0x0D0x0C0x0B0x0A0x090x080x070x060x050x040x030x020x010x00

Name

SREGSPHSPLCCPRSTFLRSMCROSCCALReservedCLKMSRCLKPSRPRRVLMCSRNVMCMDNVMCSRWDTCSRReservedGTCCRTCCR0ATCCR0BTCCR0CTIMSK0TIFR0TCNT0HTCNT0LOCR0AHOCR0ALOCR0BHOCR0BLICR0HICR0LReservedReservedACSRReservedADCSRAADCSRBADMUXReservedADCLReservedDIDR0ReservedEICRAEIFREIMSKPCICRPCIFRPCMSKReservedReservedReservedPORTCRReservedReservedReservedReservedReservedReservedReservedReservedPUEBPORTBDDRBPINB

Bit 7

I

Bit 6

T

Bit 5

H

Bit 4

S

Bit 3

V

Bit 2

N

Bit 1

Z

Bit 0

C

Page

Page 12Page 12Page 12Page 12

Stack Pointer High ByteStack Pointer Low ByteCPU Change Protection Byte

––––––VLMF–NVMBSYWDIF–TSMCOM0A1ICNC0FOC0A––

––––––VLMIE––WDIE––COM0A0ICES0FOC0B––

–WDP3––COM0B1

––ICIE0ICF0

––––COM0B0WGM03

–––

–––––––

–––––––

WDRFSM2––CLKPS3

–––WDE–––WGM02

–––

NVM Comman

–WDP2–––CS02–OCIE0BOCF0B

–WDP1––WGM01CS01–OCIE0AOCF0A

–WDP0–PSRWGM00CS00–TOIE0TOV0

–SM1––CLKPS2

–VLM2

EXTRFSM0–CLKMS1CLKPS1PRADCVLM1

PORFSE–CLKMS0CLKPS0PRTIM0VLM0

Page 35Page 25Page 21Page 21Page 22Page 26Page 34Page 116Page 116Page 32Page 80Page 74Page 76Page 77Page 79Page 80Page 78Page 78Page 78Page 78Page 78Page 78Page 79Page 79

Oscillator Calibration Byte

Timer/Counter0 – Counter Register High ByteTimer/Counter0 – Counter Register Low ByteTimer/Counter0 – Compare Register A High ByteTimer/Counter0 – Compare Register A Low ByteTimer/Counter0 – Compare Register B High ByteTimer/Counter0 – Compare Register B Low ByteTimer/Counter0 - Input Capture Register High ByteTimer/Counter0 - Input Capture Register Low Byte

––ACD–ADEN––––––––––––––––––––––––––––

––––ADSC––––––––––––––––––––––––––––

––ACO–ADATE––––––––––––––––––––––––––––

––ACI–ADIF––––––––––––––––––––––––––––

––ACIE–ADIE––––ADC3D––––––PCINT3––––––––––––PUEB3PORTB3DDRB3PINB3

––ACIC–ADPS2ADTS2–––ADC2D––––––PCINT2

––––––––––––PUEB2PORTB2DDRB2PINB2

––ACIS1–ADPS1ADTS1MUX1––ADC1D–ISC01––––PCINT1

–––BBMB––––––––PUEB1PORTB1DDRB1PINB1

––ACIS0–ADPS0ADTS0MUX0–

Page 82Page 94Page 95Page 94Page 96

ADC Conversion Result

–ADC0D–ISC00INTF0INT0PCIE0PCIF0PCINT0

––––––––––––PUEB0PORTB0DDRB0PINB0

Page 83, Page 96

Page 38Page 39Page 39Page 40Page 40Page 40

Page 51

Page 51Page 52Page 52Page 52

6

ATtiny4/5/9/10

8127ES–AVR–11/11

ATtiny4/5/9/10

Note:

1.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.2.I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.3.Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.4.The ADC is available in ATtiny5/10, only.

8127ES–AVR–11/11

7

5.Instruction Set Summary

Mnemonics

ADDADCSUBSUBISBCSBCIANDANDIORORIEORCOMNEGSBRCBRINCDECTSTCLRSERRJMPIJMPRCALLICALLRETRETICPSECPCPCCPISBRCSBRSSBICSBISBRBSBRBCBREQBRNEBRCSBRCCBRSHBRLOBRMIBRPLBRGEBRLTBRHSBRHCBRTSBRTCBRVSBRVCBRIEBRIDLSLLSRROLRORASRSWAPBSET

Rd,RrRd,RrRd,RrRd,KRr, bRr, bA, bA, bs, ks, k k k k k k k k k k k k k k k k k k kRdRdRdRdRdRdsk

Operands

Rd, RrRd, RrRd, RrRd, KRd, RrRd, KRd, RrRd, KRd, RrRd, KRd, RrRdRdRd,KRd,KRdRdRdRdRdk

Add without CarryAdd with CarrySubtract without CarrySubtract ImmediateSubtract with Carry

Description

Rd ← Rd + Rr

OperationFlags

Z,C,N,V,S,HZ,C,N,V,S,HZ,C,N,V,S,HZ,C,N,V,S,HZ,C,N,V,S,HZ,C,N,V,S,HZ,N,V,SZ,N,V,SZ,N,V,SZ,N,V,SZ,N,V,SZ,C,N,V,SZ,C,N,V,S,HZ,N,V,SZ,N,V,SZ,N,V,SZ,N,V,SZ,N,V,SZ,N,V,SNoneNoneNoneNoneNoneNoneINoneZ, C,N,V,S,HZ, C,N,V,S,HZ, C,N,V,S,HNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneZ,C,N,V,HZ,C,N,VZ,C,N,V,HZ,C,N,VZ,C,N,VNoneSREG(s)

#Clocks

11111111111111111111223/43/44/54/51/2/31 111/2/31/2/31/2/31/2/31/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21111111

ARITHMETIC AND LOGIC INSTRUCTIONS

Rd ← Rd + Rr + CRd ← Rd - RrRd ← Rd - KRd ← Rd - Rr - CRd ← Rd - K - CRd ← Rd • RrRd ← Rd • KRd ← Rd v RrRd ← Rd v KRd ← Rd ⊕ RrRd ← $FF − RdRd ← $00 − RdRd ← Rd v KRd ← Rd • ($FFh - K)Rd ← Rd + 1Rd ← Rd − 1 Rd ← Rd • Rd

Rd ← Rd ⊕ RdRd ← $FF

PC ← PC + k + 1

PC(15:0) ← Z, PC(21:16) ←0PC ← PC + k + 1

PC(15:0) ← Z, PC(21:16) ←0PC ← STACKPC ← STACK

if (Rd = Rr) PC ← PC + 2 or 3Rd − RrRd − Rr − CRd − K

if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3if (I/O(A,b)=0) PC ← PC + 2 or 3 if (I/O(A,b)=1) PC ← PC + 2 or 3if (SREG(s) = 1) then PC←PC+k + 1if (SREG(s) = 0) then PC←PC+k + 1if (Z = 1) then PC ← PC + k + 1if (Z = 0) then PC ← PC + k + 1if (C = 1) then PC ← PC + k + 1if (C = 0) then PC ← PC + k + 1if (C = 0) then PC ← PC + k + 1if (C = 1) then PC ← PC + k + 1if (N = 1) then PC ← PC + k + 1if (N = 0) then PC ← PC + k + 1if (N ⊕ V= 0) then PC ← PC + k + 1if (N ⊕ V= 1) then PC ← PC + k + 1if (H = 1) then PC ← PC + k + 1if (H = 0) then PC ← PC + k + 1if (T = 1) then PC ← PC + k + 1if (T = 0) then PC ← PC + k + 1if (V = 1) then PC ← PC + k + 1if (V = 0) then PC ← PC + k + 1if ( I = 1) then PC ← PC + k + 1if ( I = 0) then PC ← PC + k + 1Rd(n+1) ← Rd(n), Rd(0) ← 0Rd(n) ← Rd(n+1), Rd(7) ← 0Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)Rd(n) ← Rd(n+1), n=0..6

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)SREG(s) ← 1

Subtract Immediate with CarryLogical AND

Logical AND with ImmediateLogical OR

Logical OR with ImmediateExclusive OROne’s ComplementTwo’s ComplementSet Bit(s) in RegisterClear Bit(s) in RegisterIncrementDecrement

Test for Zero or MinusClear RegisterSet RegisterRelative JumpIndirect Jump to (Z)Relative Subroutine Call Indirect Call to (Z)Subroutine ReturnInterrupt ReturnCompare, Skip if EqualCompare

Compare with CarryCompare with ImmediateSkip if Bit in Register ClearedSkip if Bit in Register is SetSkip if Bit in I/O Register ClearedSkip if Bit in I/O Register is SetBranch if Status Flag SetBranch if Status Flag ClearedBranch if Equal Branch if Not EqualBranch if Carry SetBranch if Carry ClearedBranch if Same or Higher Branch if LowerBranch if MinusBranch if Plus

Branch if Greater or Equal, SignedBranch if Less Than Zero, SignedBranch if Half Carry Flag SetBranch if Half Carry Flag ClearedBranch if T Flag SetBranch if T Flag ClearedBranch if Overflow Flag is SetBranch if Overflow Flag is ClearedBranch if Interrupt EnabledBranch if Interrupt DisabledLogical Shift LeftLogical Shift RightRotate Left Through CarryRotate Right Through CarryArithmetic Shift RightSwap NibblesFlag Set

BRANCH INSTRUCTIONS

BIT AND BIT-TEST INSTRUCTIONS

8

ATtiny4/5/9/10

8127ES–AVR–11/11

ATtiny4/5/9/10

Mnemonics

BCLRSBICBIBSTBLDSECCLCSENCLNSEZCLZSEICLISESCLSSEVCLVSETCLTSEHCLH

DATA TRANSFER INSTRUCTIONSMOVLDILDLDLDLDLDLDLDLDLDLDSSTSTSTSTSTSTSTSTSTSTSINOUTPUSHPOP

Rd, RrRd, KRd, XRd, X+Rd, - XRd, YRd, Y+Rd, - YRd, ZRd, Z+Rd, -ZRd, kX, RrX+, Rr- X, RrY, RrY+, Rr- Y, RrZ, RrZ+, Rr-Z, Rrk, RrRd, AA, RrRrRd

Copy RegisterLoad ImmediateLoad Indirect

Load Indirect and Post-Increment

Rd ← Rr

Rd ←K

Rd ← (X)

Rd ← (X), X ← X + 1

NoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNone

(see specific descr. for Sleep)

(see specific descr. for WDR)

NoneNone

111/222/31/222/31/222/31112112112111221111

sA, bA, bRr, bRd, b

Operands

Flag Clear

Set Bit in I/O RegisterClear Bit in I/O Register

Description

SREG(s) ← 0 I/O(A, b) ←1I/O(A, b) ←0T ← Rr(b)Rd(b) ←TC ←1C ← 0 N ←1N ← 0 Z ←1Z ← 0 I ←1I ← 0 S ←1S ← 0 V ←1V ← 0 T ←1T ← 0 H ←1H ← 0

OperationFlags

SREG(s)NoneNoneTNoneCCNNZZIISSVVTTHH

#Clocks

111111111111111111111

Bit Store from Register to TBit load from T to RegisterSet CarryClear CarrySet Negative FlagClear Negative FlagSet Zero FlagClear Zero FlagGlobal Interrupt EnableGlobal Interrupt DisableSet Signed Test FlagClear Signed Test Flag

Set Two’s Complement Overflow.Clear Two’s Complement OverflowSet T in SREGClear T in SREG

Set Half Carry Flag in SREGClear Half Carry Flag in SREG

Load Indirect and Pre-DecrementX ← X - 1, Rd ← (X)

Load IndirectRd ← (Y)

Load Indirect and Post-IncrementRd ← (Y), Y ← Y + 1Load Indirect and Pre-DecrementY ← Y - 1, Rd ← (Y) Rd ← (Z)

Load Indirect and Post-IncrementRd ← (Z), Z ← Z+1

Load Indirect and Pre-DecrementZ ← Z - 1, Rd ← (Z)Load Indirect

Rd ← (k) Store Indirect(X) ← Rr

Store Indirect and Post-Increment(X) ← Rr, X ← X + 1

Store Indirect and Pre-DecrementX ← X - 1, (X) ← Rr

Store Indirect(Y) ← Rr

Store Indirect and Post-Increment(Y) ← Rr, Y ← Y + 1 Store Indirect and Pre-DecrementY ← Y - 1, (Y) ← RrStore Indirect

Store Indirect and Post-Increment.Store Indirect and Pre-DecrementStore Direct to SRAMIn from I/O LocationOut to I/O LocationPush Register on StackPop Register from StackBreakNo OperationSleep

Watchdog Reset

(Z) ← Rr

(Z) ← Rr, Z ← Z + 1Z ← Z - 1, (Z) ← Rr(k) ← RrRd ← I/O (A) I/O (A) ← RrSTACK ← RrRd ← STACK

(see specific descr. for Break)

Store Direct from SRAM

MCU CONTROL INSTRUCTIONSBREAKNOPSLEEPWDR

9

8127ES–AVR–11/11

6.Ordering Information

6.1

ATtiny4

Supply Voltage

Speed (1)12 MHz

1.8 – 5.5V

10 MHz

Notes:

TemperatureIndustrial(-40°C to 85°C) (4)Extended

(-40°C to 125°C) (7)

Package (2)

6ST18MA46ST1

Ordering Code (3)ATtiny4-TSHR (5)ATtiny4-MAHR (6)ATtiny4-TS8R (5)

1.For speed vs. supply voltage, see section 16.3 “Speed” on page 118.

2.All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-ous Substances (RoHS). NiPdAu finish.3.Tape and reel.

4.Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.5.Top/bottomside markings:

–Topside: T4x (x stands for “die revision”)

–Bottomside: zHzzz [H stands for (-40°C to 85°C)], z8zzz [8 stands for (-40°C to 125°C)]6.Topside marking:

–1st Line: T4–2nd Line: xx–3rd Line: xxx

7.For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125°C.

Package Type

6ST18MA4

6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)

10

ATtiny4/5/9/10

8127ES–AVR–11/11

ATtiny4/5/9/10

6.2

ATtiny5

Supply Voltage

Speed (1)12 MHz

1.8 – 5.5V

10 MHz

Notes:

TemperatureIndustrial(-40°C to 85°C) (4)Extended

(-40°C to 125°C) (7)

Package (2)

6ST18MA46ST1

Ordering Code (3)ATtiny5-TSHR (5)ATtiny5-MAHR (6)ATtiny5-TS8R (5)

1.For speed vs. supply voltage, see section 16.3 “Speed” on page 118.

2.All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-ous Substances (RoHS). NiPdAu finish.3.Tape and reel.

4.Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.5.Top/bottomside markings:

–Topside: T5x (x stands for “die revision”)

–Bottomside: zHzzz [H stands for (-40°C to 85°C)], z8zzz [8 stands for (-40°C to 125°C)]6.Topside marking:

–1st Line: T5–2nd Line: xx–3rd Line: xxx

7.For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125°C.

Package Type

6ST18MA4

6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)

11

8127ES–AVR–11/11

6.3ATtiny9

Supply Voltage

Speed (1)12 MHz

1.8 – 5.5V

10 MHz

TemperatureIndustrial(-40°C to 85°C) (4)Extended

(-40°C to 125°C) (7)

Package (2)

6ST18MA46ST1

Ordering Code (3)ATtiny9-TSHR (5)ATtiny9-MAHR (6)ATtiny9-TS8R (5)

Notes:1.For speed vs. supply voltage, see section 16.3 “Speed” on page 118.

2.All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-ous Substances (RoHS). NiPdAu finish.3.Tape and reel.

4.Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.5.Top/bottomside markings:

–Topside: T9x (x stands for “die revision”)

–Bottomside: zHzzz [H stands for (-40°C to 85°C)], z8zzz [8 stands for (-40°C to 125°C)]6.Topside marking:

–1st Line: T9–2nd Line: xx–3rd Line: xxx

7.For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125°C.

Package Type

6ST18MA4

6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)

12

ATtiny4/5/9/10

8127ES–AVR–11/11

ATtiny4/5/9/10

6.4

ATtiny10

Supply Voltage

Speed (1)12 MHz

1.8 – 5.5V

10 MHz

Notes:

TemperatureIndustrial(-40°C to 85°C) (4)Extended

(-40°C to 125°C) (7)

Package (2)

6ST18MA46ST1

Ordering Code (3)ATtiny10-TSHR (5)ATtiny10-MAHR (6)ATtiny10-TS8R (5)

1.For speed vs. supply voltage, see section 16.3 “Speed” on page 118.

2.All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-ous Substances (RoHS). NiPdAu finish.3.Tape and reel.

4.Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.5.Top/bottomside markings:

–Topside: T10x (x stands for “die revision”)

–Bottomside: zHzzz [H stands for (-40°C to 85°C)], z8zzz [8 stands for (-40°C to 125°C)]6.Topside marking:

–1st Line: T10–2nd Line: xx–3rd Line: xxx

7.For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125°C.

Package Type

6ST18MA4

6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)

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7.Packaging Information

7.1

6ST1

D654AEE1Pin #1 IDA2AA C0.10CSEATING PLANE1b2e3A1Side ViewTop ViewA2A0.10CSEATING PLANE0.25SEATING PLANEcA1CView A-ASEE VIEW BOCLView BCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLMIN A A1 A2 D E E1 Notes: 1. 2. 3. 4. This package is compliant with JEDEC specification MO-178 Variation ABDimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrustion or gate burrs shall not exceed 0.25 mm per end.Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mmDie is facing down after trim/form. NOM– – – MAX1.450.151.303.00NOTE– 0 0.90 2.80 2.90 3.00 22.60 2.80 1.50 1.60 1.750.30 0.45 0.55 0.95 BSC0.09 – 0.20 L e c b 0.30 – 0.50 3θ 0° – 8° 6/30/08 Package Drawing Contact: packagedrawings@atmel.comTITLE 6ST1, 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)GPCTAQ DRAWING NO. REV. 6ST1A 14

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7.2

8MA4

8 7 6 50.05c8x0.05ccESIDE VIEWPin 1 ID1 2 3 4DTOP VIEWAA1D2e58KCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOL A A1 D MINNOMMAXNOTEE2– – 0.60 0.00 – 0.05 1.95 1.40 1.95 2.00 1.50 2.00 2.051.602.05C0.2 b 0.20 – 0.30 D2 E E2 e K 4b1L0.80 0.90 1.00– 0.50 –0.20 – –BOTTOM VIEW L 0.20 0.30 0.40Note: 1. ALL DIMENSIONS ARE IN mm. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS COPLANARITY SHALL NOT EXCEED 0.05 mm. 3. WARPAGE SHALL NOT EXCEED 0.05 mm. 4. REFER JEDEC MO-236/MO-252TITLE Package Drawing Contact: packagedrawings@atmel.com8PAD, 2x2x0.6 mm body, 0.5 mm pitch, 0.9x1.5 mm exposed pad, Saw singulated Thermally enhanced plastic ultra thin dual flat no lead package (UDFN/USON)GPCYAG12/17/09DRAWING NO.REV.8MA4A15

8127ES–AVR–11/11

8.Errata

The revision letters in this section refer to the revision of the corresponding ATtiny4/5/9/10device.

8.1

8.1.1

ATtiny4

Rev. E

•Programming Lock Bits

1. Programming Lock Bits

Programming Lock Bits to a lock mode equal or lower than the current causes one word ofFlash to be corrupted. The location of the corruption is random.

Problem Fix / Workaround

When programming Lock Bits, make sure lock mode is not set to present, or lower levels.

8.1.2Rev. D

•ESD HBM (ESD STM 5.1) level ±1000V•Programming Lock Bits

1. ESD HBM (ESD STM 5.1) level ±1000V

The device meets ESD HBM (ESD STM 5.1) level ±1000V.

Problem Fix / Workaround

Always use proper ESD protection measures (Class 1C) when handling integrated circuitsbefore and during assembly.

2. Programming Lock Bits

Programming Lock Bits to a lock mode equal or lower than the current causes one word ofFlash to be corrupted. The location of the corruption is random.

Problem Fix / Workaround

When programming Lock Bits, make sure lock mode is not set to present, or lower levels.

8.1.3Rev. A – C

Not sampled.

8.2

8.2.1

ATtiny5

Rev. E

•Programming Lock Bits

1. Programming Lock Bits

Programming Lock Bits to a lock mode equal or lower than the current causes one word ofFlash to be corrupted. The location of the corruption is random.

Problem Fix / Workaround

When programming Lock Bits, make sure lock mode is not set to present, or lower levels.

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8.2.2

Rev. D

•ESD HBM (ESD STM 5.1) level ±1000V•Programming Lock Bits

1. ESD HBM (ESD STM 5.1) level ±1000V

The device meets ESD HBM (ESD STM 5.1) level ±1000V.

Problem Fix / Workaround

Always use proper ESD protection measures (Class 1C) when handling integrated circuitsbefore and during assembly.

2. Programming Lock Bits

Programming Lock Bits to a lock mode equal or lower than the current causes one word ofFlash to be corrupted. The location of the corruption is random.

Problem Fix / Workaround

When programming Lock Bits, make sure lock mode is not set to present, or lower levels.

8.2.3

Rev. A – C

Not sampled.

8.3

8.3.1

ATtiny9

Rev. E

•Programming Lock Bits

1. Programming Lock Bits

Programming Lock Bits to a lock mode equal or lower than the current causes one word ofFlash to be corrupted. The location of the corruption is random.

Problem Fix / Workaround

When programming Lock Bits, make sure lock mode is not set to present, or lower levels.

8.3.2Rev. D

•ESD HBM (ESD STM 5.1) level ±1000V•Programming Lock Bits

1. ESD HBM (ESD STM 5.1) level ±1000V

The device meets ESD HBM (ESD STM 5.1) level ±1000V.

Problem Fix / Workaround

Always use proper ESD protection measures (Class 1C) when handling integrated circuitsbefore and during assembly.

2. Programming Lock Bits

Programming Lock Bits to a lock mode equal or lower than the current causes one word ofFlash to be corrupted. The location of the corruption is random.

Problem Fix / Workaround

When programming Lock Bits, make sure lock mode is not set to present, or lower levels.

17

8127ES–AVR–11/11

8.3.3Rev. A – C

Not sampled.

8.4

8.4.1

ATtiny10

Rev. E

•Programming Lock Bits

1. Programming Lock Bits

Programming Lock Bits to a lock mode equal or lower than the current causes one word ofFlash to be corrupted. The location of the corruption is random.

Problem Fix / Workaround

When programming Lock Bits, make sure lock mode is not set to present, or lower levels.

8.4.2Rev. C – D

•ESD HBM (ESD STM 5.1) level ±1000V•Programming Lock Bits

1. ESD HBM (ESD STM 5.1) level ±1000V

The device meets ESD HBM (ESD STM 5.1) level ±1000V.

Problem Fix / Workaround

Always use proper ESD protection measures (Class 1C) when handling integrated circuitsbefore and during assembly.

2. Programming Lock Bits

Programming Lock Bits to a lock mode equal or lower than the current causes one word ofFlash to be corrupted. The location of the corruption is random.

Problem Fix / Workaround

When programming Lock Bits, make sure lock mode is not set to present, or lower levels.

8.4.3Rev. A – B

Not sampled.

18

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9.Datasheet Revision History

9.1

Rev. 8127E – 11/11

1.Updated:

–Device status from Preliminary to Final

–Ordering information on page 154, page 155, page 156, and page 157

9.2Rev. 8127D – 02/10

1.Added UDFN package in “Features” on page 1, “Pin Configurations” on page 2, “Order-ing Information” on page 154, and in “Packaging Information” on page 1582.Updated Figure 8-2 and Figure 8-3 in Section 8.2.1 “Power-on Reset” on page 283.Updated Section 8.2.3 “External Reset” on page 29

4.Updated Figures 17-36 and 17-51 in “Typical Characteristics”

5.Updated notes in Section 20. “Ordering Information” on pages 154- 1576.Added device Rev. E in Section 22. “Errata” on page 160

9.3Rev. 8127C – 10/09

1.Updated values and notes:

–Table 16-1 in Section 16.2 “DC Characteristics” on page 117–Table 16-3 in Section 16.4 “Clock Characteristics” on page 119–Table 16-6 in Section 16.5.2 “VCC Level Monitor” on page 120

–Table 16-9 in Section 16.8 “Serial Programming Characteristics” on page 1222.Updated Figure 16-1 in Section 16.3 “Speed” on page 118

3.Added Typical Characteristics Figure 17-36 in Section 17.8 “Analog Comparator Offset”

on page 141. Also, updated some other plots in Typical Characteristics.4.Added topside and bottomside marking notes in Section 20. “Ordering Information” on

page 154, up to page 1575.Added ESD errata, see Section 22. “Errata” on page 160

6.Added Lock bits re-programming errata, see Section 22. “Errata” on page 160

9.4Rev. 8127B – 08/09

1.Updated document template

2.Expanded document to also cover devices ATtiny4, ATtiny5 and ATtiny93.Added section:

–“Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10” on page 44.Updated sections:

–“ADC Clock – clkADC” on page 18

–“Starting from Idle / ADC Noise Reduction / Standby Mode” on page 20–“ADC Noise Reduction Mode” on page 24–“Analog to Digital Converter” on page 25

–“SMCR – Sleep Mode Control Register” on page 25–“PRR – Power Reduction Register” on page 26–“Alternate Functions of Port B” on page 49

19

8127ES–AVR–11/11

–“Overview” on page 84

–“Physical Layer of Tiny Programming Interface” on page 97–“Overview” on page 108

–“ADC Characteristics (ATtiny5/10, only)” on page 121–“Supply Current of I/O Modules” on page 123–“Register Summary” on page 150–“Ordering Information” on page 1545.Added figure:

–“Using an External Programmer for In-System Programming via TPI” on page 986.Updated figure:

–“Data Memory Map (Byte Addressing)” on page 157.Added table:

–“Number of Words and Pages in the Flash (ATtiny4/5)” on page 1108.Updated tables:

–“Active Clock Domains and Wake-up Sources in Different Sleep Modes” on page 23–“Reset and Interrupt Vectors” on page 36

–“Number of Words and Pages in the Flash (ATtiny9/10)” on page 110–“Signature codes” on page 111

9.5Rev. 8127A – 04/09

1.Initial revision

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21

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8127ES–AVR–11/11