ics9248-192

Systems, Inc.

ICS9248-192

Frequency Timing Generator for Transmeta SystemsRecommended Application:TransmetaOutput Features:•1CPU(2.5V or 3.3V selectable) up to 66.6MHz &overclocking of 66MHz.••••6 PCI (3.3V) @ 33.3MHz (all are free runningselectable).1 REF (3.3V) at 14.318MHz.1 48MHz (3.3V).1 24_48MHz selectable output.Pin ConfigurationGNDREFX1X2PD#PCICLK0PCICLK1PCICLK2GNDPCIVDDPCIPCICLK3PCICLK4PCICLK5SDATASCLK12345671011121314Features:•Supports Spread Spectrum modulation for CPU andPCI clocks, default -0.4 downspread.•Efficient Power management scheme through stopclocks and power down modes.•Uses external 14.318MHz crystal, no external loadcap required for CL=18pF crystal.•28-pin TSSOP package, 4.40mm (173mil).Skew Characteristics:•CPU – CPU <175ps•PCI – PCI < 500ps•CPU(early) – PCI = 1.5ns – 4ns.2827262524232221201918171615VDDREFREFCPU_STOP#VDDLCPUGNDLCPUCPUCLK0PCI_STOP#GND_CoreVDD_CoreSEL66/60#VDD48GND4848MHz/CPU3.3v_2.5V#sel24-48MHz/Sel48_24#28-Pin TSSOPBlock DiagramPLL2/ 2X1X2XTALOSCPLL1SpreadSpectrum48MHz24_48MHzREFCPUDIVDERStopCPUCLK0SEL48_24#CPU3.3V_2.5V#selSEL66/60#PD#PCI_STOP#CPU_STOP#SDATASCLKControlLogicConfig.Reg.PCIDIVDERStop6PCICLK (5:0)Power GroupsVDD_Core, GND_Core = PLL coreVDDREF, GNDREF = REF, X1, X2VDDPCI, GNDPCI = PCICLK (5:0)VDD48, GND48 = 48MHz (1:0)0540E—08/20/03ICS9248-192ICS9248-192

Pin DescriptionsPin number 123412, 11, 10, 7, 6, 515131418MHz1718GND48VDD48OutputPowerPowerPin nameGNDREFX1X2PD#PCICLK (5:0)GNDPCIVDDPCISel48_24#24_48MHzSDATASCLKCPU3.3-2.5#TypePowerInputOutputInputOutputPowerPowerInputOutputI/OINInputDescriptionGround for 14.318 MHz reference clock outputs14.318 MHz crystal input14.318 MHz crystal outputAsynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms.3.3V PCI clock outputs, free running selectable Ground for PCI clock outputs3.3V power for the PCI clock outputsSelects 24MHz (0) or 48MHz (1) outputSelectable output either 24MHz or 48MHzData pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant 3.3 (1) or 2.5 (0) VDD buffer strength selection, has pullup to VDD, nominal 30K resistor.3.3V 48 MHz clock output, fixed frequency clock typically used with USB devicesGround for 48 MHz clocks3.3V power for 48/24 MHz clocksControl for the frequency of clocks at the CPU & PCICLK output pins. \"0\" = 60 MHz. \"1\" = 66.6 MHz. The PCI clock is multiplexed to run at 33.3 MHz for both selected cases.Isolated 3.3V power for coreIsolated ground for coreSynchronous active low input used to stop the PCICLK in active low state. It will not effect PCICLK_F or any other outputs.CPU clock outputs selectable 2.5V or 3.3V.Ground for CPU clock outputs2.5V or 3.3V power for CPU clock outputsAsynchronous active low input pin used to stop the CPUCLK in active low state, all other clocks will continue to run. The CPUCLK will have a \"Turnon \" latency of at least 3 CPU clocks. 3.3V 14.318 MHz reference clock output 3.3V power for 14.318 MHz reference clock outputs.19SEL 66/60#Input202122232425262728VDD_CoreGND_CorePCI_Stop#CPUCLK0GNDLCPUVDDLCPUCPU_STOP#REFVDDREFPowerPowerInputOutputPowerPowerInputOutputPower0540E—08/20/032

ICS9248-192

CPU Select Functions

SEL66/60#01CPU(MHz)60MHz66.6MHzPower ManagementClock Enable Configuration

CPU_STOP#X0011PCI_STOP#X0101PWR_DWN#01111CPUCLKLowLowLow60/66.6MHz60/66.6MHzPCICLKLowLow33.3MHzLow33.3MHzREFStoppedRunningRunningRunningRunningCrystalOffRunningRunningRunningRunningVCOsOffRunningRunningRunningRunningFull clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. Duringpower up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that ofthe running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clocknetwork charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.

ICS9248-192 Power Management Requirements

SIGNALCPU_STOP#PCI_STOP#PD#SIGNALSTATE0(Disabled)21(Enabled)10(Disabled)21(Enabled)11(NormalOperation)30(PowerDown)4LatencyNo.ofrisingedgesoffreerunningPCICLK11113ms2maxNotes.

1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only. The REF will be stopped independant of these.

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ICS9248-192

The information in this section assumes familiarity with I2C programming.For more information, contact ICS for an I2C programming application note.General I2C serial interface informationHow to Write:Controller (host) sends a start bit.Controller (host) sends the write address D2 (H)ICS clock will acknowledgeController (host) sends a dummy command codeICS clock will acknowledgeController (host) sends a dummy byte countICS clock will acknowledgeController (host) starts sending first byte (Byte 0)through byte 6•ICS clock will acknowledge each byte one at a time.•Controller (host) sends a Stop bitHow to Write:Controller (Host)Start BitAddressD2(H)Dummy Command CodeICS (Slave/Receiver)How to Read:••••••••Controller (host) will send start bit.Controller (host) sends the read address D3 (H)ICS clock will acknowledgeICS clock will send the byte countController (host) acknowledgesICS clock sends first byte (Byte 0) through byte 6Controller (host) will need to acknowledge each byteController (host) will send a stop bit••••••••How to Read:Controller (Host)Start BitAddressD3(H)ICS (Slave/Receiver)ACKACKDummy Byte CountACKByte CountACKACKByte 0Byte 0ACKByte 1ACKByte 1ACKByte 2ACKByte 2ACKByte 3ACKByte 3ACKByte 4ACKByte 4ACKByte 5ACKByte 5ACKByte 6ACKByte 6ACKStop BitACKStop BitNotes:1.2.3.4.5.The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches forverification. Read-Back will support Intel PIIX4 \"Block-Read\" protocol.The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)The input is operating at 3.3V logic levels.The data byte format is 8 bit bytes.To simplify the clock generator I2C interface, the protocol is set to use only \"Block-Writes\" from the controller.The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after anycomplete byte has been transferred. The Command code and Byte count shown above must be sent, but thedata is ignored for those two bytes. The data is loaded until a Stop sequence is issued.At power-on, all registers are set to a default condition, as shown.6.0540E—08/20/034

ICS9248-192

Serial Configuration Command BitmapByte0: Functionality and Frequency Select Register (default = 0)BitBit2FS40000000000000000Bit2,7:41111111111111111Bit7FS300000000111111110000000011111Bit6FS200001111000011110000111100001Bit5FS100110011001100110011001100110Bit4FS001010101010101010101010101010CPU6060606066.666.666.666.667.3268.69.9672.661.563656066.6504858.857.656.4546060606066.6PCI3030303033.333.333.333.333.6634.3234.9836.330.7531.53232.53033.3252429.428.828.2273030303033.3Spread % -0.4 % down spread-0.6 % down spread-0.8 % down spread-1.0 % down spread -0.4 % down spread-0.6 % down spread-0.8 % down spread-1.0 % down spread 2% over-clocking 4% over-clocking 6% over-clocking 10% over-clocking over-clocking over-clocking over-clocking over-clocking+/- 0.5% center spread+/- 0.5% center spreadunder-clockingunder-clocking2% under-clock4% under-clock6% under-clock10% under-clock -1.4 % down spread-1.6 % down spread-1.8 % down spread-2.0 % down spread -1.4 % down spreadPWD00000Bit3Bit1Bit066.633.3-1.6 % down spread110166.633.3-1.8 % down spread111066.633.3-2.0 % down spread1111Hardware latch inputs can only access these frequencies0-Frequency is seleced by hardware select. Latched input1-Frequency is seleced by Bit 2, 7:40-Normal 1-Spread spectrun Enabled0-Running 1-Tristate all outputs000Note: PWD = Power-Up Default0540E—08/20/035

ICS9248-192

Byte 1: PCI StopByte 2: Stop Clocks

BITBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0PIN#121110765--PWD111111XXDESCRIPTIONPCICLK5PCICLK4PCICLK3PCICLK2PCICLK1PCICLK0ReservedReservedBITBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0PIN#16152327----PWD1111XXXXDESCRIPTION48MHz48_24MHzCPUCLK0REFReservedReservedReservedReservedNote:

1 = Inactive0 = Active

Byte 3:Free-Running Enable

Note:

1 = Inactive0 = ActiveByte 4: Reserved

BITBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0PIN#121110765--PWD111111XXDESCRIPTIONPCICLK5PCICLK4PCICLK3PCICLK2PCICLK1PCICLK0ReservedReservedBITPIN#PWDBit7-XBit6-XBit5-XBit4-XBit3-XBit2-XBit1-XBit0-XDESCRIPTIONReservedReservedReservedReservedReservedReservedReservedReservedNote:

0 = Not free-running (controlled by PCI_STOP# pin)1 = Free-running (can override Byte1 PCI Stop Control)Byte 5: Reserved

Byte 6: Reserved

BITPIN#PWDBit7-XBit6-XBit5-XBit4-XBit3-XBit2-XBit1-XBit0-XDESCRIPTIONReservedReservedReservedReservedReservedReservedReservedReservedBITPIN#PWDBit7-0Bit6-0Bit5-0Bit4-0Bit3-0Bit2-1Bit1-1Bit0-0DESCRIPTIONReservedReservedReservedReservedReservedReservedReservedReservedNote: PWD = Power-Up Default

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ICS9248-192

CPU_STOP# Timing DiagramCPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.CPU_STOP# is synchronized by the ICS9248-192. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse)is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always bestopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latencyis less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.INTERNALCPUCLKPCICLKCPU_STOP#PCI_STOP#(High)PD#(High)CPUCLKNotes:1. All timing is referenced to the internal CPUCLK.2. CPU_STOP# is an asynchronous input and metastable conditions mayexist. This signal is synchronized to the CPUCLKs inside the ICS9248-192.3. All other clocks continue to run undisturbed.4. PD# and PCI_STOP# are shown in a high (true) state.PCI_STOP# Timing DiagramPCI_STOP# is an asynchronous input to the ICS9248-192. It is used to turn off the PCICLK clocks for low poweroperation. PCI_STOP# is synchronized by the ICS9248-192 internally. The minimum that the PCICLK clocks areenabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and startedwith a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latencyis one PCICLK clock.Notes:1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-192 device.)2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248-192.3. All other clocks continue to run undisturbed.4. PD# and CPU_STOP# are shown in a high (true) state.0540E—08/20/037

ICS9248-192

PD# Timing DiagramThe power down selection is used to put the part into a very low power state without turning off the power to the part.PD# is an asynchronous active low input. This signal is synchronized internally by the ICS9248-192 prior to its controlaction of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power downstate. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystaloscillator. The power on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLKcycles. PCI_STOP# and CPU_STOP# are don’t care signals during the power down operations.CPUCLK(Internal)PCICLK(Internal)PD#CPUCLKPCICLK_F,PCICLKREFINTERNALVCOsINTERNALCRYSTALOSC.Notes:1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.0540E—08/20/038

ICS9248-192

Absolute Maximum RatingsSupply Voltage. . . . . . . . . . . . . . . . . . . . . . . 5.5 VLogic Inputs. . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 VAmbient Operating Temperature. . . . . . . . . . 0°C to +70°CStorage Temperature. . . . . . . . . . . . . . . . . . . –65°C to +150°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseratings are stress specifications only and functional operation of the device at these or any other conditions above thoselisted in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditionsfor extended periods may affect product reliability.Electrical Characteristics - Input/Supply/Common Output ParametersTA = 0 - 70°C; Supply Voltage VDDL = 2.5V, VDD = 3.3 V +/-5% (unless otherwise stated)PARAMETERInput High VoltageInput Low VoltageInput High CurrentInput Low CurrentInput Low CurrentOperating Supply CurrentPower DownSupply CurrentInput frequencyInput Capacitance1Transition Time1Clk Stabilization1Skew11SYMBOLVIHVILIIHIIL1IIL2IDD2.5OP66IDD3.3OP66IDD3.3PDFiCINCINXTtransTSTABTCPU-PCICONDITIONSMIN2VSS - 0.3-5-200TYPVIN = VDDVIN = 0 V; Inputs with no pull-up resistorsVIN = 0 V; Inputs with pull-up resistorsCL = 0 pF; Select @ 66.6MHzCL = 0 pF; Select @ 66.6MHzCL = 0 pF; With input address to Vdd or GNDVDD = 3.3 V;Logic InputsX1 & X2 pinsTo 1st crossing of target Freq.From VDD = 3.3 V to 1% target Freq.VT = 1.5 V; VTL = 1.25 VMAXUNITSVDD + 0.3V0.8V5mAmAmA15mA80mAµA6001654533MHzpFpFmsmsns112714.3181.54Guaranteed by design, not 100% tested in production.0540E—08/20/039

ICS9248-192

Electrical Characteristics - CPUCLKTA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)PARAMETEROutput High VoltageOutput Low VoltageOutput High CurrentOutput Low CurrentRise TimeFall TimeDuty CycleSkewJitter1SYMBOLVOH2BVOL2BIOH2BIOL2Btr2B1tf2B1dt2B1tsk2B1CONDITIONSIOH = -12.0 mAIOL = 12 mAVOH = 1.7 VVOL = 0.7 VVOL = 0.4 V, VOH = 2.0 VVOH = 2.0 V, VOL = 0.4 VVT = 1.25 VVT = 1.25 VMIN1.8TYP270.40.444MAXUNITSV0.4V-27mAmA1.61.655175250nsns%pspspstjcyc-cyc2B1VT = 1.25 Vtjabs2B1VT = 1.25 V-250+250Guaranteed by design, not 100% tested in production.Electrical Characteristics - REFTA = 0 - 70°C; VDD = 3.3 V , VDDL = 2.5V, +/-5%; CL = 10 - 20 pF (unless otherwise stated)PARAMETEROutput High VoltageOutput Low VoltageOutput High CurrentOutput Low CurrentRise Time1Fall Time1Duty Cycle1Jitter1Jitter1SYMBOLVOH5VOL5IOH5IOL5tr5tf5dt5tjcyc-cyc5tjabs5tjcyc-cyc5tjabs5CONDITIONSIOH = -12 mAIOL = 9 mAVOH = 2.0 VVOL = 0.8 VVOL = 0.4 V, VOH = 2.4 VVOH = 2.4 V, VOL = 0.4 VVT = 1.5 VVT = 1.5 V, REFVT = 1.5 V, REFVT = 1.5 V, 48 MHzVT = 1.5 V, 48 MHz45MIN2.6TYPMAXUNITSV0.4V-22mAmA44551000800500800nsns%pspspsps160540E—08/20/0310

ICS9248-192

Electrical Characteristics - 48MHzTA = 0 - 70°C; VDD = 3.3 V , VDDL = 2.5V, +/-5%; CL = 10 - 20 pF (unless otherwise stated)PARAMETEROutput High VoltageOutput Low VoltageOutput High CurrentOutput Low CurrentRise Time1Fall Time1Duty Cycle1Jitter1Jitter1SYMBOLVOH5VOL5IOH5IOL5tr5tf5dt5tjcyc-cyc5tjabs5tjcyc-cyc5tjabs5CONDITIONSIOH = -12 mAIOL = 9 mAVOH = 2.0 VVOL = 0.8 VVOL = 0.4 V, VOH = 2.4 VVOH = 2.4 V, VOL = 0.4 VVT = 1.5 VVT = 1.5 V, REFVT = 1.5 V, REFVT = 1.5 V, 48 MHzVT = 1.5 V, 48 MHz45MIN2.6TYPMAXUNITSV0.4V-22mAmA1.21.2551000800500800nsns%pspspsps16Electrical Characteristics - PCICLKTA = 0 - 70°C; VDD = 3.3 V, VDDL = 2.5V +/-5%; CL = 30 pFPARAMETEROutput High VoltageOutput Low VoltageOutput High CurrentOutput Low CurrentRise Time1Fall TimeSkew1Jitter11SYMBOLVOH1VOL1IOH1IOL1tr1tf1dt1tsk1tjcyc-cyc1tjabs1CONDITIONSIOH = -18 mAIOL = 9.4 mAVOH = 2.0 VVOL = 0.8 VVOL = 0.4 V, VOH = 2.4 VVOH = 2.4 V, VOL = 0.4 VVT = 1.5 VVT = 1.5 VVT = 1.5 VVT = 1.5 VMIN2.1TYP16MAXUNITSV0.4V-22mA57mA22nsns%pspspsDuty Cycle14555500500500Guaranteed by design, not 100% tested in production.0540E—08/20/0311

ICS9248-192

NcSYMBOLIn MillimetersIn InchesCOMMON DIMENSIONSCOMMON DIMENSIONSMINMAX1.200.151.050.30MIN-.002.032.007MAX.047.006.041.012-0.050.800.19LAA1A2bcDEINDEXAREAE1E0.090.20SEE VARIATIONS6.40 BASIC4.304.500.65 BASIC0.450.75SEE VARIATIONS0°-8°0.10.0035.008SEE VARIATIONS0.252 BASIC.169.1770.0256 BASIC.018.030SEE VARIATIONS0°-8°.00412DαE1eLNαA2A1AaaaVARIATIONS-C-N28D mm.MIN9.60MAX9.80MIN.378D (inch)MAX.3867/6/00 Rev CebSEATINGPLANEaaaCMO-153 JEDECDoc.# 10-00354.40 mm. Body, 0.65 mm. pitch TSSOP(0.0256 Inch)(173 mil)Ordering InformationICS9248yG-192-TExample:ICS XXXX y G - PPP - TDesignation for tape and reel packagingPattern Number (2 or 3 digit number for parts with ROM codepatterns)Package Type G = TSSOPRevision Designator (will not correlate with datasheet revision)Device Type (consists of 3 or 4 digit numbers)Prefix ICS, AV = Standard Device0540E—08/20/0312